Datasheet > ISL12022MA_10

ISL12022MA_10

更新时间： 2022-12-17 23:47:37

品牌	Logo	应用领域
英特矽尔 - INTERSIL		电池温度补偿静态存储器
页数	文件大小	规格书
29页	860K
描述
Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

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ISL12022MA_10 数据手册

ISL12022MA

DC Operating Characteristics RTC Test Conditions: V

= +2.7 to +5.5V, T = -40°C to +85°C, unless otherwise

stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

MIN TYP MAX

SYMBOL

PARAMETER

Temperature Sensor Accuracy

(OPEN DRAIN OUTPUT)

Output Low Voltage

CONDITIONS

= V = 3.3V

(Note 7) (Note 8) (Note 7) UNITS NOTES

Temp

±2

°C

BAT

IRQ/F

OUT

= 5V, I

= 3mA

= 1mA

0.4

= 2.7V, I

Power-Down Timing Test Conditions: V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.

Boldface limits apply over the operating temperature range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

(Note 7) (Note 8) (Note 7) UNITS NOTES

Negative Slew Rate

10 V/ms 12

DDSR-

I2C Interface Specifications Test Conditions: V

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise

specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 7)

(Note 8) (Note 7) UNITS NOTES

SDA and SCL Input

Buffer LOW Voltage

-0.3

0.3 x V

SDA and SCL Input

Buffer HIGH Voltage

0.7 x V

+ 0.3

Hysteresis SDA and SCL Input

Buffer Hysteresis

0.05 x V

0.02

13, 14

SDA Output Buffer

LOW Voltage, Sinking

3mA

= 5V, I

DD OL

= 3mA

0.4

SDA and SCL Pin

Capacitance

T = +25°C, f = 1MHz,

= 5V, V = 0V,

= 0V

OUT

SCL Frequency

400

kHz

SCL

Pulse Width

Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the max

spec is suppressed.

SCL Falling Edge to

SDA Output Data Valid V , until SDA exits the 30% to

SCL falling edge crossing 30% of

900

70% of V

window.

Time the Bus Must be SDA crossing 70% of V

during a

1300

BUF

Free Before the Start of STOP condition, to SDA crossing

a New Transmission

Clock LOW Time

Clock HIGH Time

70% of V

START condition.

during the following

Measured at the 30% of V

crossing.

1300

600

LOW

Measured at the 70% of V

crossing.

HIGH

START Condition Setup SCL rising edge to SDA falling edge.

Time Both crossing 70% of V

SU:STA

HD:STA

START Condition Hold From SDA falling edge crossing

Time 30% of V to SCL falling edge

crossing 70% of V

FN7575.1

July 9, 2010

1...3 4 567 8 9...29

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