®
IS93C46A
IS93C56A
IS93C66A
ISSI
PIN CONFIGURATIONS
8-Pin DIP
8-Pin JEDEC SOIC “GR”
8-Pin JEDEC SOIC “G”
NC
VCC
CS
1
2
3
4
8
7
6
5
ORG
GND
CS
SK
1
2
3
4
8
7
6
5
VCC
NC
CS
SK
1
2
3
4
8
7
6
5
VCC
NC
DOUT
IN
DIN
ORG
GND
DIN
ORG
GND
SK
D
D
OUT
D
OUT
(Rotated)
instruction begins with a start bit of the logical “1” or
HIGH. Following this are the opcode (2 bits),
address field (6, 7, or 8 bits), and data, if appropriate.
The clock signal may be held stable at any moment to
suspend the device at its last state. This allows clock-
speed flexibility as well as maximum power
conservation.
PIN DESCRIPTIONS
CS
Chip Select
SK
Serial Data Clock
Serial Data Input
Serial Data Output
OrganizationSelect
NotConnected
Power
DIN
DOUT
ORG
NC
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the DOUT pin. After the read instruction and
address have been decoded, data is transferred from the
selectedmemoryregisterintoa serialshiftregister.(Please
note that one logical “0” bit precedes the actual 8 or 16-bit
outputdatastring.)TheoutputonDOUT changesduringthe
low-to-high transitions of SK (see Figure 3).
Vcc
GND
Ground
Applications
The IS93C46A/56A/66A is very popular in many high-
volumeapplicationswhichrequirelow-power,low-
density storage. Applications using this device include
DVD players, modems, pc mainboards, LAN cards, and
Low Voltage Read
TheIS93C46A/56A/66Ahavebeendesignedtoensurethat
data read operations are reliable in low voltage environ-
ments. They provide accurate operation with Vcc as low
as 2.5V.
numerous other consumer electronics.
Endurance and Data Retention
Auto Increment Read Operations
TheIS93C46A/56A/66Aisdesignedforapplicationsrequir-
ingupto1Mprogramming cycles(WRITE,WRALL,ERASE
and ERAL). It provides 40 years of secure data retention,
withoutpoweraftertheexecutionof1Mprogrammingcycles.
In the interest of memory transfer operation applications,
the IS93C46A/56A/66A has been designed to output a
continuous stream of memory content in response to a
singlereadoperationinstruction.Toutilizethisfunction,the
systemassertsareadinstructionspecifyingastartlocation
address.Oncethe8or16bitsoftheaddressedregisterhave
been clocked out, the data in consecutively higher address
locations is output. The address will wrap around continu-
ously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
Device Operations
The IS93C46A/56A/66A are controlled by a set of
instructions which are clocked-in serially on the Din pin.
Before each low-to-high transition of the clock (SK), the
CS pin must have already been raised to HIGH, and the
Din value must be stable at either LOW or HIGH. Each
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATIONRev. 00A
05/07/02
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