Datasheet > IS64LF12836A-7.5B3LA3

IS64LF12836A-7.5B3LA3

更新时间： 2024-10-02 14:51:39

品牌	Logo	应用领域
美国芯成 - ISSI		时钟静态存储器内存集成电路
页数	文件大小	规格书
25页	520K
描述
Cache SRAM, 128KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, TFBGA-165

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技术参数
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IS64LF12836A-7.5B3LA3 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	TBGA, BGA165,11X15,40	Reach Compliance Code：	compliant
风险等级：	5.76	最长访问时间：	7.5 ns
最大时钟频率 (fCLK)：	117 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	功能数量：	1
端子数量：	165	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
筛选级别：	AEC-Q100	座面最大高度：	1.2 mm
最大待机电流：	0.045 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.175 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	13 mm
Base Number Matches：	1

IS64LF12836A-7.5B3LA3 数据手册

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IS61(64)LF12832A IS64VF12832A

IS61(64)LF12836A IS61(64)VF12836A

IS61(64)LF25618A IS61(64)VF25618A

128K x 32, 128K x 36, 256K x 18

4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEBRUARY 2014

FEATURES

DESCRIPTION

The ISSIꢀ IS61(64)LF12832A,ꢀIS64VF12832A,ꢀIS61(64)

LF/VF12836AꢀandꢀIS61(64)LF/VF25618Aꢀarehigh-speed,

low-power synchronous static RAMs designed to provide

burstable, high-performance memory for communication

and networking applications. The IS61(64)LF12832A is

organizedꢀasꢀ131,072ꢀwordsꢀbyꢀ32ꢀbits.ꢀTheꢀIS61(64)LF/

VF12836Aꢀisꢀorganizedꢀasꢀ131,072ꢀwordsꢀbyꢀ36ꢀbits.ꢀThe

IS61(64)LF/VF25618Aꢀisꢀorganizedꢀasꢀ262,144ꢀwordsꢀbyꢀ

18ꢀbits.ꢀFabricatedꢀwithꢀISSI'sꢀadvancedꢀCMOSꢀtechnol-

ogy, thedeviceintegratesa2-bitburstcounter, high-speed

SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ

control

•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ

•ꢀ Three chip enable option for simple depth expan-

sion and address pipelining

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ AutoꢀPower-downꢀduringꢀdeselect

•ꢀ Singleꢀcycleꢀdeselect

Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ

theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀoneꢀ

to four bytes wide as controlled by the write control inputs.

•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby

•ꢀ PowerꢀSupply

Separate byte enables allow individual bytes to be written.

Byteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀbyteꢀwriteꢀen-

ableꢀ(BWE) input combined with one or more individual

byteꢀwriteꢀsignalsꢀ(BWx). Inꢀaddition,ꢀGlobalꢀWriteꢀ(GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

LF: V^dd3.3V + 5%, Vddq 3.3V/2.5V + 5%

VF: V^dd2.5V -5% +10%, Vddq 2.5V -5% +10%

•ꢀ JEDECꢀ100-PinꢀQFP,ꢀ119-pinꢀBGA,ꢀandꢀ165-pinꢀ

BGAꢀpackages

•ꢀ Automotiveꢀtemperatureꢀavailable

•ꢀ Lead-freeꢀavailable

BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSPꢀ(AddressꢀStatusꢀ

Processor) or ADSCꢀ(AddressꢀStatusꢀCacheꢀController)ꢀ

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the ADVꢀ(burstꢀaddressꢀ

advance) input pin.

The mode pin is used to select the burst sequence order,

LinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀInterleaveꢀ

burstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀorꢀleftꢀﬂoating.

FAST ACCESS TIME

Symbol

Parameter

-6.5

6.5ꢀ

7.5ꢀ

133ꢀ

-7.5

7.5ꢀ

8.5ꢀ

117ꢀ

Units

tkq

tkc

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

ꢀ

Frequencyꢀ

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

Rev. G1

2/11/2014

12 3 4 5 6 7...25

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与IS64LF12836A-7.5B3LA3相关器件

型号	品牌	获取价格	描述	数据表
IS64LF12836A-7.5TQA3	ISSI	获取价格	128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS64LF12836EC-6.5B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836EC-6.5B2LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836EC-6.5B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836EC-6.5B3LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836EC-6.5TQA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836EC-6.5TQLA3	ISSI	获取价格	Cache SRAM, 128KX36, 6.5ns, CMOS, PQFP100, TQFP-100
IS64LF12836EC-7.5B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836EC-7.5B2LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64LF12836EC-7.5B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM

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