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IS61LPS102436B-200TQLI-TR PDF预览

IS61LPS102436B-200TQLI-TR

更新时间： 2024-02-02 20:43:59
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
35页 1227K
描述
IC SRAM 36M PARALLEL 100LQFP

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IS61LPS102436B-200TQLI-TR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：LQFP,
Reach Compliance Code：compliantFactory Lead Time：10 weeks
风险等级：5.8最长访问时间：3.1 ns
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：37748736 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mm

IS61LPS102436B-200TQLI-TR 数据手册

 浏览型号IS61LPS102436B-200TQLI-TR的Datasheet PDF文件第2页浏览型号IS61LPS102436B-200TQLI-TR的Datasheet PDF文件第3页浏览型号IS61LPS102436B-200TQLI-TR的Datasheet PDF文件第4页浏览型号IS61LPS102436B-200TQLI-TR的Datasheet PDF文件第5页浏览型号IS61LPS102436B-200TQLI-TR的Datasheet PDF文件第6页浏览型号IS61LPS102436B-200TQLI-TR的Datasheet PDF文件第7页 
wordsꢀbyꢀ32ꢀbits.  
                                                                   
36ꢀbits.ꢀTheꢀIS61LPS102432Bꢀisꢀorganizedꢀasꢀ1,048,476ꢀ  
TheꢀIS61LPS/VPS204818Bꢀisꢀorganizedꢀ  
                                                             
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B  
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B  
1M x 36, 1M x 32, 2M x 18  
36 Mb SYNCHRONOUS PIPELINED,  
SINgLE CYCLE DESELECT STATIC RAM  
NOVEMBER 2017  
FEATURES  
DESCRIPTION  
Theꢀ36Mbꢀproductꢀfamilyꢀfeaturesꢀ high-speed,ꢀlow-powerꢀ  
synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀburstable,ꢀ  
high-performanceꢀ memoryꢀ forꢀ communicationꢀ andꢀ net-  
workingꢀapplications.ꢀTheꢀIS61LPS/VPS102436Bꢀandꢀ  
IS64LPS102436Bꢀareꢀorganizedꢀasꢀ1,048,476ꢀwordsꢀbyꢀ  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ  
control  
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ  
asꢀ2,096,952ꢀwordsꢀbyꢀ18ꢀbits.ꢀFabricatedꢀwithꢀISSI'sꢀ  
advancedꢀ CMOSꢀ technology,ꢀ theꢀ deviceꢀ integratesꢀ aꢀ  
2-bitꢀburstꢀcounter,ꢀhigh-speedꢀSRAMꢀcore,ꢀandꢀhigh-  
driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀmonolithicꢀcircuit.ꢀAllꢀ  
synchronousꢀinputsꢀpassꢀthroughꢀregistersꢀcontrolledꢀbyꢀ  
aꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.  
•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-  
pansionꢀandꢀaddressꢀpipelining  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ AutoꢀPower-downꢀduringꢀdeselect  
•ꢀ Singleꢀcycleꢀdeselect  
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ  
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ  
oneꢀtoꢀfourꢀbytesꢀwideꢀasꢀcontrolledꢀbyꢀtheꢀwriteꢀcontrolꢀ  
inputs.  
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackage  
•ꢀ PowerꢀSupply  
Separateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀwritten.ꢀ  
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ  
writeꢀenableꢀ(BWE)ꢀinputꢀcombinedꢀwithꢀoneꢀorꢀmoreꢀ  
individualꢀbyteꢀwriteꢀsignalsꢀ(BWx). Inꢀaddition,ꢀGlobalꢀ  
Writeꢀ(GW)ꢀisꢀavailableꢀforꢀwritingꢀallꢀbytesꢀatꢀoneꢀtime,ꢀ  
regardlessꢀofꢀtheꢀbyteꢀwriteꢀcontrols.  
ꢀ LPS:ꢀVdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)  
VPS:ꢀVdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)  
VVPS:ꢀVdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)  
•ꢀ JEDECꢀ100-PinꢀQFP,ꢀ119-ballꢀBGA,ꢀandꢀ165-  
ballꢀBGAꢀpackages  
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSPꢀ(AddressꢀStatusꢀ  
Processor)ꢀorꢀADSCꢀ(AddressꢀStatusꢀCacheꢀController)ꢀ  
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-  
atedꢀinternallyꢀandꢀcontrolledꢀbyꢀtheꢀADVꢀ(burstꢀaddressꢀ  
advance)ꢀinputꢀpin.ꢀ  
•ꢀ Lead-freeꢀavailable  
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-  
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ  
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ  
orꢀleftꢀfloating.  
FAST ACCESS TIME  
Symbol  
tkq  
Parameter  
250  
2.8  
4
200  
3.1  
5
166  
Units  
ns  
Clock Access Time  
Cycle Time  
3.8  
6
tkc  
ns  
Frequency  
250  
200  
166  
MHz  
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. C  
11/03/2017  
1234567...35

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