IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSI
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
PRELIMINARY INFORMATION
FEBRUARY 2005
DESCRIPTION
FEATURES
The ISSIIS61(64)LPS12832A,IS61(64)LPS/VPS12836A
andIS61(64)LPS/VPS25618Aarehigh-speed,low-power
synchronous static RAMs designed to provide burstable,
high-performancememoryforcommunicationandnetwork-
ingapplications.TheIS61(64)LPS12832Aisorganizedas
131,072wordsby32bits.TheIS61(64)LPS/VPS12836A
isorganizedas131,072wordsby36bits.TheIS61(64)LPS/
VPS25618A is organized as 262,144 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology, the
deviceintegratesa2-bitburstcounter,high-speedSRAM
core,andhigh-drivecapabilityoutputsintoasinglemono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
Write cycles are internally self-timed and are initiated by
therisingedgeoftheclockinput. Writecyclescanbeone
tofourbyteswideascontrolledbythewritecontrolinputs.
• Snooze MODE for reduced-power standby
• Power Supply
Separatebyteenablesallowindividualbytestobewritten.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, and
165-ball PBGA packages
• Automotive temperature available
• Lead Free available
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
inputpins.Subsequentburstaddressescanbegenerated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
250
2.6
4
200
3.1
5
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
250
200
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
1
10/07/04