Datasheet > IS42LS81600A

IS42LS81600A

更新时间： 2022-12-12 14:37:32

品牌	Logo	应用领域
矽成 - ICSI		动态存储器
页数	文件大小	规格书
66页	553K
描述
16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

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IS42LS81600A 数据手册

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

ISSI

DEVICE OVERVIEW

to hide precharge time and the capability to randomly

changecolumnaddressesoneachclockcycleduringburst

access.

The 128Mb SDRAM is a high speed CMOS, dynamic

random-access memory designed to operate in 2.5V VDD

and1.8VVDDQ or 3.3VDD and3.3VVDDQ memorysystems

containing 134,217 ,728 bits. Internally configured as a

quad-bank DRAM with a synchronous interface. Each

16,777,216-bit bank is organized as 4,096 rows by 256

columns by 16 bits.

A self-timed row precharge initiated at the end of the burst

sequence is available with the AUTO PRECHARGE func-

tionenabled. Prechargeonebankwhileaccessingoneofthe

otherthreebankswillhidetheprechargecyclesandprovide

seamless,high-speed,random-accessoperation.

The128MbSDRAMincludesanAUTOREFRESHMODE,

and a power-saving, power-down mode. All signals are

registeredonthepositiveedgeoftheclocksignal,CLK. All

inputs and outputs are LVTTL compatible.

SDRAMreadandwriteaccessesareburstorientedstartingat

aselectedlocationandcontinuingforaprogrammednum-

ber of locations in a programmed sequence. The registra-

tionofanACTIVEcommandbeginsaccesses, followedby

a READ or WRITE command. The ACTIVE command in

conjunction with address bits registered are used to select

the bank and row to be accessed (BA0, BA1 select the

bank; A0-A11 select the row). The READ or WRITE

commands in conjunction with address bits registered are

used to select the starting column location for the burst

access.

Only partials of the memory array can be selected for Self-

Refresh and the refresh period during Self-Refresh is

progammable in 4 steps which drastically reduces the self

refresh current, depending on the case temperature of the

components in the system application.

The 128Mb SDRAM has the ability to synchronously burst

data at a high data rate with automatic column-address

generation,theabilitytointerleavebetweeninternalbanks

ProgrammableREADorWRITEburstlengthsconsistof1,

2, 4 and 8 locations or full page, with a burst terminate

option.

FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

RAS

CAS

DQM

DATA IN

BUFFER

COMMAND

DECODER

CLOCK

GENERATOR

REFRESH

CONTROLLER

MODE

I/O 0-15

A11

Vcc/Vcc

SELF

DATA OUT

BUFFER

REFRESH

GND/GNDQ

A10

CONTROLLER

REFRESH

COUNTER

4096

BA0

BA1

4096

MEMORY CELL

ARRAY

4096

BANK 0

ROW

ADDRESS

LATCH

ROW

ADDRESS

BUFFER

SENSE AMP I/O GATE

256K

(x 16)

COLUMN

ADDRESS LATCH

BANK CONTROL LOGIC

BURST COUNTER

COLUMN DECODER

COLUMN

ADDRESS BUFFER

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

06/01/02

123 4 5 6 7...66

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与IS42LS81600A相关器件

型号	品牌	描述	获取价格	数据表
IS42LS81600A-10T	ICSI	16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM	获取价格
IS42LS81600A-10TI	ICSI	16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM	获取价格
IS42LS81600A-7T	ICSI	16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM	获取价格
IS42LS81600A-7TI	ICSI	16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM	获取价格
IS42LS81600AL-10T	ISSI	Synchronous DRAM, 16MX8, 7ns, CMOS, PDSO54, TSOP2-54	获取价格
IS42LS81600AL-10TL	ISSI	Synchronous DRAM, 16MX8, 7ns, CMOS, PDSO54, LEAD FREE, TSOP2-54	获取价格

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