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IS41LV16100A PDF预览

IS41LV16100A

更新时间: 2024-02-01 06:57:06
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
22页 143K
描述
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IS41LV16100A 数据手册

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®
IS41LV16100A  
1M x 16 (16-MBIT) DYNAMIC RAM  
WITH EDO PAGE MODE  
ISSI  
MARCH2005  
FEATURES  
DESCRIPTION  
• TTL compatible inputs and outputs; tristate I/O  
TheISSIIS41LV16100Ais1,048,576x16-bithigh-perfor-  
manceCMOS DynamicRandomAccessMemories. These  
devices offer an accelerated cycle access called EDO  
Page Mode. EDO Page Mode allows 1,024 random ac-  
cesses within a single row with access cycle time as short  
as 20 ns per 16-bit word.  
• Refresh Interval:  
— Auto refresh Mode: 1,024 cycles /16 ms  
RAS-Only, CAS-before-RAS (CBR), and Hidden  
• JEDEC standard pinout  
ThesefeaturesmaketheIS41LV16100Aideallysuited for  
high-bandwidthgraphics, digitalsignalprocessing, high-  
performance computing systems, and peripheral  
applications.  
• Single power supply:  
— 3.3V ± 10% (IS41LV16100A)  
• Byte Write and Byte Read operation via two CAS  
• Industrial Temperature Range: -40oC to +85oC  
• Lead-free available  
The IS41LV16100A is packaged in a 42-pin 400-mil SOJ  
and 400-mil 50- (44-) pin TSOP (Type II).  
KEY TIMING PARAMETERS  
Parameter  
-50  
50  
-60  
60  
Unit  
ns  
PIN CONFIGURATIONS  
Max. RAS Access Time (tRAC)  
Max. CAS Access Time (tCAC)  
50(44)-Pin TSOP (Type II)  
42-PinSOJ  
14  
15  
ns  
Max. Column Address Access Time (tAA) 25  
30  
ns  
VDD  
I/O0  
I/O1  
I/O2  
I/O3  
VDD  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
GND  
I/O15  
I/O14  
I/O13  
I/O12  
GND  
I/O11  
I/O10  
I/O9  
VDD  
I/O0  
I/O1  
I/O2  
I/O3  
VDD  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
1
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
GND  
I/O15  
I/O14  
I/O13  
I/O12  
GND  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
Min. EDO Page Mode Cycle Time (tPC)  
Min. Read/Write Cycle Time (tRC)  
30  
85  
40  
ns  
2
2
3
3
110  
ns  
4
4
5
5
6
6
7
PIN DESCRIPTIONS  
7
8
8
9
A0-A9  
I/O0-15  
WE  
Address Inputs  
DataInputs/Outputs  
WriteEnable  
9
10  
11  
I/O8  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
NC  
NC  
NC  
WE  
RAS  
NC  
NC  
A0  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
NC  
NC  
LCAS  
UCAS  
OE  
LCAS  
UCAS  
OE  
WE  
RAS  
NC  
OE  
OutputEnable  
A9  
RAS  
UCAS  
LCAS  
VDD  
RowAddressStrobe  
A9  
NC  
A8  
A8  
UpperColumnAddressStrobe  
LowerColumnAddressStrobe  
Power  
A0  
A7  
A7  
A1  
A6  
A1  
A6  
A2  
A5  
A2  
A5  
A3  
A4  
A3  
A4  
VDD  
GND  
VDD  
GND  
GND  
NC  
Ground  
NoConnection  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. B  
1
03/02/05  

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