Datasheet > IS41C44002-50J

IS41C44002-50J

更新时间： 2024-01-20 08:50:58

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
19页	159K
描述
4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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技术参数
数据手册

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IS41C44002-50J 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2, TSOP24/26,.36
针数：	24	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.92	访问模式：	FAST PAGE WITH EDO
最长访问时间：	50 ns	其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e0	长度：	17.14 mm
内存密度：	16777216 bit	内存集成电路类型：	EDO DRAM
内存宽度：	4	功能数量：	1
端口数量：	1	端子数量：	24
字数：	4194304 words	字数代码：	4000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装等效代码：	TSOP24/26,.36
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	刷新周期：	2048
座面最大高度：	1.2 mm	自我刷新：	NO
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.12 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

IS41C44002-50J 数据手册

IS41C4400X

IS41LV4400X SERIES

ISSI

Functional Description

Auto Refresh Cycle

The IS41C4400x and IS41LV4400x are CMOS

DRAMs optimized for high-speed bandwidth, low

power applications. During READ or WRITE cycles, each

bit is uniquely addressed through the 11 or 12 address

bits. These are entered 11 bits (A0-A10) at a time for the

2K refresh device or 12 bits (A0-A11) at a time for the 4K

refresh device. The row address is latched by the Row

Address Strobe (RAS). The column address is latched by

the Column Address Strobe (CAS). RAS is used to latch

the first nine bits and CAS is used the latter ten bits.

To retain data, 2,048 refresh cycles are required in each

32 ms period, or 4,096 refresh cycles are required in

each 64ms period. There are two ways to refresh the

memory:

1. By clocking each of the 2,048 row addresses (A0

through A10) or 4096 row addresses (A0 through

A11) with RAS at least once every 32 ms or 64ms

respectively. Any read, write, read-modify-write or

RAS-only cycle refreshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS

refresh is activated by the falling edge of RAS, while

holding CAS LOW. In CAS-before-RAS refresh cycle,

an internal 9-bit counter provides the row addresses

and the external address inputs are ignored.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum t^RAStime has expired. A new

cycle must not be initiated until the minimum precharge

time tRP, tCP has elapsed.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Power-On

Read Cycle

After application of the VCC supply, an initial pause of 200

µs is required followed by a minimum of eight initialization

cycles (any combination of cycles containing a RAS

signal).

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time

specified by tAR. Data Out becomes valid only when tRAC,

tAA, tCAC and tOEA are all satisfied. As a result, the access

time is dependent on the timing relationships between

these parameters.

During power-on, it is recommended that RAS track with

VCC or be held at a valid VIH to avoid current surges.

Write Cycle

A write cycle is initiated by the falling edge of CAS and

WE, whichever occurs last. The input data must be valid

at or before the falling edge of CAS or WE, whichever

occurs last.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

06/24/01

1 234 5 6 7...19

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与IS41C44002-50J相关器件

型号	品牌	描述	获取价格	数据表
IS41C44002-50JI	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44002-50T	ETC	x4 EDO Page Mode DRAM	获取价格
IS41C44002-50TI	ISSI	EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, TSOP2-24	获取价格
IS41C44002-60J	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44002-60JI	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44002-60T	ISSI	EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, TSOP2-24	获取价格

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