IRU1050
Assuming the following specifications:
Air Flow (LFM)
100 200
0
300
400
VIN = 5V
Thermalloy
AAVID
6021PB 6021PB 6073PB 6109PB 7141D
534202B 534202B 507302 575002 576802B
VOUT = 3.5V
IOUT(MAX) = 4.6A
TA = 358C
Note: For further information regarding the above com-
The steps for selecting a proper heat sink to keep the panies and their latest product offerings and application
junction temperature below 1358C is given as:
support contact your local representative or the num-
bers listed below:
1) Calculate the maximum power dissipation using:
AAVID.................PH# (603) 528 3400
Thermalloy...........PH# (214) 243-4321
PD = IOUT×(VIN - VOUT)
PD = 4.6×(5 - 3.5) = 6.9W
Designing for Microprocessor Applications
2) Select a package from the regulator data sheet and As it was mentioned before, the IRU1050 is designed
record its junction to case (or tab) thermal resistance. specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
Selecting TO-220 package gives us:
of 2.5V to 3.6V generated by stepping down the 5V sup-
ply. These processors demand a fast regulator that sup-
ports their large load current changes. The worst case
θJC = 2.78C/W
3) Assuming that the heat sink is black anodized, cal- current step seen by the regulator is anywhere in the
culate the maximum heat sink temperature allowed: range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from “Stop
Assume, θcs=0.05°C/W (heat-sink-to-case thermal Clock” mode to the “Full Active” mode. The load current
resistance for black anodized)
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however, the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
TS = TJ - PD×(θJC + θCS)
TS = 135 - 6.9×(27 + 0.05) = 1168C
4) With the maximum heat sink temperature calculated frequency low ESR and low ESL output capacitor is
in the previous step, the heat-sink-to-air thermal re- imperative in the design of these regulator circuits.
sistance (θSA) is calculated by first calculating the
temperature rise above the ambient as follows:
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the (∆VESR=ESR×∆I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (∆VESL
=L×∆I/∆t). The output capacitance effect is a droop in
∆T = TS - TA = 116 - 35 = 818C
DT = Temperature Rise Above Ambient
81
6.9
∆T
PD
θSA =
=
= 11.78C/W
5) Next, a heat sink with lower θSA than the one calcu- the output voltage proportional to the time it takes for
lated in Step 4 must be selected. One way to do this the regulator to respond to the change in the current,
is to simply look at the graphs of the “Heat Sink Temp (∆Vc=∆t×∆I/C) where ∆t is the response time of the
Rise Above the Ambient” vs. the “Power Dissipation” regulator.
and select a heat sink that results in lower tempera-
ture rise than the one calculated in previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Rev. 1.8
08/20/02
www.irf.com
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