IRU1030
Assuming the following specifications:
Air Flow (LFM)
0
100
Thermalloy 6109PB 6110PB
AAVID
200
300
VIN = 3.3V
VOUT = 1.5V
IOUT(MAX) = 2.7A
TA = 358C
7141
7178
575002 507302 576802B 577102
The steps for selecting a proper heat sink to keep the Note: For further information regarding the above com-
junction temperature below 135°C is given as:
panies and their latest product offerings and application
support contact your local representative or the num-
bers listed below:
1) Calculate the maximum power dissipation using:
PD = IOUT×(VIN - VOUT)
AAVID................PH# (603) 528 3400
Thermalloy..........PH# (214) 243-4321
PD = 2.7×(3.3 - 1.5) = 4.86W
2) Select a package from the regulator data sheet and Designing for Microprocessor Applications
record its junction to case (or tab) thermal resistance. As it was mentioned before the IRU1030 is designed
specifically to provide power for the new generation of
Selecting TO-220 package gives us:
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V
supply. These processors demand a fast regulator that
θJC = 2.78C/W
3) Assuming that the heat sink is black anodized, cal- supports their large load current changes. The worst case
culate the maximum heat sink temperature allowed: current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
Assume, θcs=0.05°C/W (heat-sink-to-case thermal could happen when the processor transitions from “Stop
resistance for black anodized)
Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
TS = TJ - PD×(θJC + θCS)
TS = 135 - 4.86×(2.7 + 0.05) = 121.78C
4) With the maximum heat sink temperature calculated levels. Because of this requirement the selection of high
in the previous step, the heat-sink-to-air thermal re- frequency low ESR and low ESL output capacitors is
sistance (θSA) is calculated by first calculating the imperative in the design of these regulator circuits.
temperature rise above the ambient as follows:
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
∆T = TS - TA = 121.7 - 35 = 86.78C
DT=Temperature Rise Above Ambient
∆T 86.7
the ESR of the output capacitor produces an instanta-
neous drop equal to the (DVESR=ESR×DI) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (DVESL
θSA =
=
= 17.88C/W
PD
4.86
5) Next, a heat sink with lower θSA than the one calcu- =L×DI/Dt). The output capacitance effect is a droop in
lated in step 4 must be selected. One way to do this the output voltage proportional to the time it takes for the
is to simply look at the graphs of the “Heat Sink Temp regulator to respond to the change in the current,
Rise Above the Ambient” vs. the “Power Dissipation” (DVc=Dt×DI/C) where Dt is the response time of the
and select a heat sink that results in lower tempera- regulator.
ture rise than the one calculated in the previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Rev. 1.3
08/20/02
www.irf.com
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