Datasheet > IP100

IP100

更新时间： 2024-09-26 23:58:39

品牌	Logo	应用领域
其他 - ETC		控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
92页	2521K
描述
PCI 10/100M Single Chip Ethernet Controller

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IP100 数据手册

IP100

Integrated 10/100 Ethernet MAC + PHY

Features

General description

The IP100 is a single-chip, full duplex, 10/100Mbps

Ethernet MAC + PHY incorporating a 32-bit PCI with

bus master support. The IP100 is designed for use in a

variety of applications including workstation NICs, PC

motherboards, and other systems utilizing a PCI bus

that require network connectivity to an Ethernet or Fast

Ethernet LAN.

ꢀ

Single chip 10/100BASE, half or full duplex

Ethernet Media Access Controller

IEEE 802.3 compliant 100BASE-TX PHY

IEEE 802.3 compliant 10BASE-T PHY

IEEE 802.3 full duplex flow control

IEEE 802.3 compliant 100BASE-FX PCS

and PMA

ꢀ

PCI Bus master scatter/gather DMA on any

byte boundary

Full operation with PCI Clock from 12.5

MHz to 33 MHz

PCI Revision 2.2 compliant

On-chip transmit and receive FIFO buffers

On-chip LED drivers

Power management capabilities for ACPI

1.0 compliant systems

The IP100 includes a PCI bus interface unit, IEEE

802.3 compliant MAC, transmit and receive FIFO

buffers, IEEE 802.3 compliant 100BASE-TX,

10BASE-T, and 100BASE-FX PHY, serial EEPROM

interface, expansion ROM interface, and LED drivers.

ꢀ

The IP100 implements a rich set of control and status

registers. Accessible via the PCI interface, these

registers provide a host system visibility into the

features and operating state of the IP100. Network

management statistics are also recorded, and host

access to registers of the PHY device are facilitated

through the IP100’s PCI interface.

ꢀ

WakeOnLAN support

Management statistics gathering

IP multicast receive and filter support using

64 bit hash table

ꢀ

Transmit polling

The IP100 supports features for use in “Green PCs” or

systems where control over system power

consumption is desired. The IP100 supports several

power down states, and the ability to issue a system

“wake event” via reception of unique, user defined

Ethernet frames. In addition, the IP100 can assert a

wake event in response to changes in the Ethernet link

status.

Auto pad insertion for short packets

Programmable minimum Inter Packet Gap

Programmable transmit and receive FIFO

watermarks

On-chip crystal oscillator

On-chip voltage regulator

2.5/3.3V CMOS with 5V tolerant I/O

0.25µm technology

128-pin PQFP

ꢀ

1/92

IP100-DS-R03

May 27, 2003

Preliminary, Specification subject to change without notice.

12 3 4 5 6 7...92

中文翻译

下载PDF

与IP100相关器件

型号	品牌	获取价格	描述	数据表
IP1000ALF	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R01	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R02	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R03	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R04	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R05	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R06	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R07	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R08	ETC	获取价格	Gigabit Ethernet NIC Single Chip
IP1001	INFINEON	获取价格	Full Function Synchronous Buck Power Block

与IP100相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

19
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

16
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

18
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

28

产品中心

服务支持

精选活动

关于我们

帮助中心

IP100

IP100 数据手册

与IP100相关器件

与IP100相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IP100

IP100 数据手册

与IP100相关器件

与IP100相关文章

您还可以找

您在本页遇到什么问题？