IP1001

更新时间： 2024-09-26 22:33:43

品牌	Logo	应用领域
英飞凌 - INFINEON		电源电路
页数	文件大小	规格书
18页	506K
描述
Full Function Synchronous Buck Power Block

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IP1001 数据手册

PD - 94336c

iP1001

Full Function Synchronous Buck Power Block

Integrated Power Semiconductors, Control IC & Passives

Features

• 3.3V to 12V input voltage1

• 20A maximum load capability, with no derating up to T_PCB= 90°C

• 5 bit DAC settable, 0.925V to 2V output voltage range 2

• Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit 3

• 200kHz or 300kHz nominal switching frequency

• Optimized for very low power losses

• Over & undervoltage protection

• Adjustable lossless current limit

• Internal features minimize layout sensitivity *

• Very small outline 14mm x 14mm x 3mm

iP1001 Power Block

Description

The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.

The iP1001 is optimized for single-phase applications, and includes a full function fast transient response

PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark

power density. Very few external components are required, including output inductor, input & output capacitors.

Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and

operation up to 3.3Vout can be achieved with a simple external voltage divider.

iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high

power densities. iPOWIR technology eases design for applications where component integration offers

benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,

heat transfer and component selection.

iP1001 Internal Block Diagram

V_IN

5 Bit

DAC

V_SW

PWM

& Driver

ENABLE

PGOOD

ILIM

FREQ

V_DD

PGND

V_FSV_F

SGND

GNDS

* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be

applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The

iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable

and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.

www.irf.com

05/20/03

12 3 4 5 6 7...18

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与IP1001相关器件

型号	品牌	获取价格	描述	数据表
IP1001-DS-R01	ETC	获取价格	Integrated 10/100/1000 Gigabit Ethernet Transceiver
IP1001-DS-R02	ETC	获取价格	Integrated 10/100/1000 Gigabit Ethernet Transceiver
IP1001-DS-R03	ETC	获取价格	Integrated 10/100/1000 Gigabit Ethernet Transceiver
IP1001-DS-R04	ETC	获取价格	Integrated 10/100/1000 Gigabit Ethernet Transceiver
IP1001-DS-R05	ETC	获取价格	Integrated 10/100/1000 Gigabit Ethernet Transceiver
IP1001-DS-R06	ETC	获取价格	Integrated 10/100/1000 Gigabit Ethernet Transceiver
IP1001LF	ETC	获取价格	Integrated 10/100/1000 Gigabit Ethernet Transceiver
IP1001PBF	INFINEON	获取价格	DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SSBGA-218
IP100ALF	ETC	获取价格	Integrated 10/100 Ethernet MAC + PHY
IP101	ETC	获取价格	PHY 10/100M Single Chip Fast Ethernet Transceiver

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