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INA-34063-TR1 PDF预览

INA-34063-TR1

更新时间: 2024-01-25 12:17:37
品牌 Logo 应用领域
安捷伦 - AGILENT 射频微波
页数 文件大小 规格书
11页 75K
描述
Wide Band Low Power Amplifier, 100MHz Min, 3000MHz Max, BIPolar, SOT-363, 6 PIN

INA-34063-TR1 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.1特性阻抗:50 Ω
增益:18 dB最大输入功率 (CW):7 dBm
最大工作频率:3000 MHz射频/微波设备类型:WIDE BAND LOW POWER
最大电压驻波比:1.1Base Number Matches:1

INA-34063-TR1 数据手册

 浏览型号INA-34063-TR1的Datasheet PDF文件第2页浏览型号INA-34063-TR1的Datasheet PDF文件第3页浏览型号INA-34063-TR1的Datasheet PDF文件第4页浏览型号INA-34063-TR1的Datasheet PDF文件第5页浏览型号INA-34063-TR1的Datasheet PDF文件第6页浏览型号INA-34063-TR1的Datasheet PDF文件第7页 
3.0 GHz Medium Power Silicon  
RFIC Amplifier  
Technical Data  
INA-34063  
Features  
Surface Mount SOT-363  
( SC-70) Package  
Description  
• +8 dBm P1 dB at 1.9 GHz  
Agilents INA-34063 is a Silicon  
RFIC amplifier that offers  
excellent gain and output power  
for applications to 3.0 GHz.  
Packaged in an ultraminiature  
SOT-363 package, it requires half  
of the board space of a SOT-143  
package.  
• 21 dB Gain at 1.9 GHz  
• High Isolation 32 dB at  
1.9 GHz  
• Single +3V Supply  
• Unconditionally Stable  
Applications  
Pin Connections and  
Package Marking  
With its wide bandwidth and high  
linearity, the INA-34063 is  
suitable as a driver amplifier for  
various applications. The  
INA-34063 also features high  
reverse isolation, making it an  
excellent candidate for LO buffer  
applications.  
• LO Buffer and Driver  
Amplifier for Cellular,  
Cordless, Special Mobile  
Radio, PCS, ISM, Wireless  
LAN, DBS, TVRO, and TV  
Tuner  
GND 2 1  
GND 1 2  
INPUT 3  
6
OUTPUT  
& V  
d
5 GND 1  
4 V  
d
Note: Package marking provides  
orientation and identification.  
The INA-34063 is fabricated using  
Agilents 30 GHzfmax,  
ISOSAT™ Silicon-bipolar process  
that uses nitride, self-alignment,  
submicrometer lithography,  
trench isolation, ion implantation,  
and polyimide intermetal dielec-  
tric and scratch protection to  
achieve superior performance,  
uniformity and reliability.  
Simplified Schematic  
V
d
Output & V  
d
Input  
Gnd1  
Gnd2  

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