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IMSH2GS13A1F1CT16H PDF预览

IMSH2GS13A1F1CT16H

更新时间: 2023-01-03 04:50:11
品牌 Logo 应用领域
奇梦达 - QIMONDA 动态存储器双倍数据速率
页数 文件大小 规格书
41页 844K
描述
DDR DRAM Module, 256MX64, CMOS, GREEN, SO-DIMM-204

IMSH2GS13A1F1CT16H 数据手册

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Advance Internet Data Sheet  
IMSH[1G/2G]S1[3/4]A1F1C(T)  
DDR3 SO-DIMM Modules  
1
Overview  
This chapter gives an overview of the 204–pin Small-Outlined DDR3 Dual-In-Line memory modules product family and  
describes its main characteristics.  
1.1  
Features  
204-pin 8-Byte DDR3 SDRAM Small-Outlined Dual-In-  
Line Memory Modules .  
Module organization: 128M × 64, 256M × 64  
Chip organization: 64M × 16, 128M × 8.  
PC3-12800, PC3-10600 and PC3-8500 module speed  
grades.  
2-GB and 1-GB modules built with 1-Gbit DDR3 SDRAMs  
in packages PG-TFBGA-78 and PG-TFBGA-96.  
DDR3 SDRAMs with a single 1.5 V (± 0.075 V) power  
supply.  
On-Die-Termination (ODT) and Dynamic ODT for  
improved signal integrity.  
Refresh, Self Refresh and Power Down Modes.  
ZQ Calibration for output driver and ODT.  
System Level Timing Calibration Support via Write  
Leveling and Multi Purpose Register (MPR) Read Pattern.  
Serial Presence Detect with EEPROM  
Thermal sensor functionality.  
SO-DIMM dimensions: 67.6 mm x 30 mm.  
Based on standard reference raw cards: 'A', and 'F'  
RoHS compliant products1).  
Asynchronous Reset.  
Programmable CAS Latency, CAS Write Latency, Additive  
Latency, Burst Length and Burst Type.  
TABLE 1  
Performance Table for DDR3–1600, DDR3–1333 and DDR3–1066  
QAG Speed Code  
Module Speed Bin  
Device Speed Bin  
CL-nRCD-nRP  
–16H  
–13G  
–13H  
–10F  
–10G  
8500G  
1066G  
8-8-8  
Unit  
Note  
1)  
PC3–  
–12800H  
–1600H  
9-9-9  
10600G  
1333G  
8-8-8  
10600H  
1333H  
9-9-9  
8500F  
1066F  
7-7-7  
DDR3–  
CL and CWL settings for maximum  
clock frequency  
CL = 9  
CWL = 8  
CL = 8  
CWL = 7  
CL = 9  
CWL = 7  
CL = 7  
CWL = 6  
CL = 8  
CWL = 6  
MHz  
Maximum Clock Frequency  
and Data Rate  
800  
1600  
667  
1333  
667  
1333  
533  
1066  
533  
1066  
MHz  
Mb/s  
with above CL and CWL settings  
Minimum Clock Frequency  
and Data Rate  
667  
1333  
533  
1066  
533  
1066  
400  
800  
400  
800  
MHz  
Mb/s  
with above CL and CWL settings  
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also  
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements  
from CL setting as well as requirements from CWL setting. For details, refer to Chapter 4.1 Speed Bins.  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit  
www.qimonda.com/green_products .  
Rev. 0.64, 2008-11  
3
01102008-EWLC-AP2C  

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