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IMP708RCSA PDF预览

IMP708RCSA

更新时间： 2024-01-26 05:38:38
品牌 Logo 应用领域
IMP 光电二极管监控
页数 文件大小 规格书
8页 227K
描述
3/3.3/4.0V レP SUPERVISOR CIRCUITS

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IMP708RCSA 技术参数

生命周期：Contact Manufacturer包装说明：SOP, SOP8,.25
Reach Compliance Code：unknown风险等级：5.69
Is Samacsys：N可调阈值：NO
JESD-30 代码：R-PDSO-G8端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：1.2/5.5 V
认证状态：Not Qualified子类别：Power Management Circuits
最大供电电流 (Isup)：0.14 mA表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL阈值电压标称：+3.08V
Base Number Matches：1

IMP708RCSA 数据手册

 浏览型号IMP708RCSA的Datasheet PDF文件第2页浏览型号IMP708RCSA的Datasheet PDF文件第3页浏览型号IMP708RCSA的Datasheet PDF文件第4页浏览型号IMP708RCSA的Datasheet PDF文件第5页浏览型号IMP708RCSA的Datasheet PDF文件第7页浏览型号IMP708RCSA的Datasheet PDF文件第8页 
IMP706P/R/S/T/J, IMP708R/S/T/J  
Detail Descriptions  
width is 0.5µs with a 3V VCC input and 0.15µs with a 5V VCC  
input. If not used, tie MR to VCC or leave floating.  
RESET/RESET Operation  
The RESET/RESET signals are designed to start or return a  
µP/µC to a known state.  
By connecting the watchdog output (WDO) and MR, a watchdog  
timeout forces a RESET to be generated.  
With VCC above 1.2V, RESET and RESET are guaranteed to be  
asserted. During a power-up sequence, the reset outputs remain  
asserted until the supply rises above the threshold level. The  
resets are deasserted approximately 200ms after crossing the  
threshold.  
Watchdog Timer  
A watchdog timer available on the IMP706P/R/S/T/J monitors  
µP/µC activity. If activity is not detected within 1.6 seconds on the  
Watchdog Input (WDI), the internal timer puts the Watchdog  
Output (WDO) into a LOW state. WDO will remain LOW until  
activity is detected at WDI.  
In a brownout situation where VCC falls below the threshold level,  
the reset outputs are asserted. If a brownout occurs during an  
already initiated reset period, the reset period will extend for an  
additional reset period of 200ms.  
The watchdog function is disabled, meaning it is cleared and not  
counting, if WDI is floated or connected to a three-stated circuit.  
The watchdog timer is also disabled if RESET is asserted. When  
RESET becomes inactive and the WDI input sees a high or low  
transition as short as 100ns (VCC = 2.7V)/50ns (VCC = 4.5V), the  
watchdog timer will begin a 1.6 second countdown. Additional  
transitions at WDI will reset the watchdog timer and initiate a  
new countdown sequence.  
The IMP708 devices have dual reset outputs, one active LOW and  
one active HIGH. The IMP706P has a single active HIGH reset and  
the IMP706/R/S/T/J devices have an active LOW reset output.  
IMP Part RESET Polarity Threshold Watchdog Timer  
IMP706P  
IMP706R  
IMP706S  
IMP706T  
IMP706J  
IMP708R  
IMP708S  
IMP708T  
IMP708J  
HIGH  
2.63V  
2.63V  
2.93V  
3.08V  
4.00V  
2.63V  
2.93V  
3.08V  
4.00V  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
LOW  
WDO will also become LOW and remain so, whenever the supply  
voltage, VCC, falls below the device threshold level. WDO goes HIGH  
as soon as VCC transitions above the threshold. There is no minimum  
pulse width for WDO as there is for the RESET outputs. If WDI is float-  
ed, WDO essentially acts as a low supply voltage output indicator.  
LOW  
LOW  
LOW  
Both: HIGH & LOW  
Both: HIGH & LOW  
Both: HIGH & LOW  
Both: HIGH & LOW  
No  
Power-failure detection with auxiliary comparator  
No  
All devices have an auxiliary comparator with 1.25V trip point.  
The output, PFO, is active LOW and the noninverting input is PFI.  
This comparator can be used as a supply voltage monitor with an  
external resistor voltage divider. As the monitored voltage level  
falls, PFI is reduced causing the PFO output to go LOW.  
Normally PFO interrupts the processor so the system can be shut  
down in a controlled manner.  
No  
Manual Reset (MR)  
The active-LOW manual reset input is pulled high by an internal  
20kΩ pull-up resistor and can be driven low by CMOS/TTL logic  
or a mechanical switch to ground. An external debounce circuit is  
unnecessary since the 140ms minimum reset time will debounce  
mechanical pushbutton switches. The minimum MR input pulse  
5V  
vRT  
V
CC  
0V  
tRS  
tRS  
5V  
0V  
5V  
WDI  
RESET  
MR  
0V  
tWD  
tWD  
tWP  
5V  
0V  
5V  
0V  
MR externally  
set low  
WDO  
tMD  
tWD  
tMR  
5V  
0V  
5V  
0V  
WDO  
RESET  
RESET triggered by MR  
706P_04.eps  
706P_05.eps  
Watchdog Timing  
WDI Three-state operation  
408-432-9100/www.impweb.com  
© 1999 IMP, Inc.  
6
1...345678

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