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IMP690AC/D

更新时间： 2024-01-06 20:01:07
品牌 Logo 应用领域
IMP 电池微处理器监控
页数 文件大小 规格书
10页 227K
描述
レP POWER SUPPLY SUPERVISOR WITH BATTERY BACKUP SWITCH

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中文翻译

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IMP690AC/D 技术参数

生命周期：Obsolete包装说明：DIP, DIP8,.3
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-CDIP-T8端子数量：8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：1.1/5.5 V
认证状态：Not Qualified子类别：Power Management Circuits
最大供电电流 (Isup)：0.1 mA表面贴装：NO
技术：CMOS端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

IMP690AC/D 数据手册

 浏览型号IMP690AC/D的Datasheet PDF文件第2页浏览型号IMP690AC/D的Datasheet PDF文件第3页浏览型号IMP690AC/D的Datasheet PDF文件第4页浏览型号IMP690AC/D的Datasheet PDF文件第6页浏览型号IMP690AC/D的Datasheet PDF文件第7页浏览型号IMP690AC/D的Datasheet PDF文件第8页 
IMP690A, 692A, 802L, 802M, 805L  
Application Information  
Microprocessor Interface.  
Reset Output  
The IMP690 has logic-LOW RESET output while the IMP805 has  
an inverted logic-HIGH RESET output. Microprocessors with bi-  
directional reset pins (69HC11 for example) can pose a problem  
when the supervisory circuit and the microprocessor output pins  
attempt to go to opposite logic states. The problem can be  
resolved by placing a 4.7kΩ resistor between the RESET output  
and the microprocessor reset pin. This is shown in Figure 3. Since  
the series resistor limits drive capabilities, the reset signal to other  
devices should be buffered.  
It is important to initialize a microprocessor to a known state in  
response to specific events that could create code execution errors  
and “lock-up”. The reset output of these supervisory circuits send  
a reset pulse to the microprocessor in response to power-up,  
power-down/power-loss or a watchdog time-out. The reset pulse  
width, tRS, is typically around 200ms and is LOW for the  
IMP690A, IMP692A, IMP802 and HIGH for the IMP805L.  
Power-up reset occurs when a rising VCC reaches the reset thresh-  
old, V , forcing a reset condition in which the reset output is  
RT  
asserted in the appropriate logic state for the duration of tRS  
.
Figure 2 shows the reset pin timing.  
+5V  
Power-loss or “brown-out” reset occurs when VCC dips below the  
V
CC  
reset threshold resulting in a reset assertion for the duration of tRS  
The reset signal remains asserted as long as V is between V  
.
RT  
+0V  
+5V  
+0V  
+5V  
CC  
and 1.1V, the lowest V for which these devices can provide a  
CC  
V
guaranteed logic-low output. To ensure logic inputs connected to  
the IMP690A/692A/802 RESET pin are in a known state when  
OUT  
3.0V  
tRS  
VCC is under 1.1V, a 100kΩ pull-down resistor at RESET is needed:  
the logic-high IMP805L will need a pull-up resistor to V  
.
CC  
RESET  
+0V  
+5V  
+0V  
A Watchdog time-out reset occurs when a logic “1” or logic “0” is  
continuously applied to the WDI pin for more than 1.6 seconds.  
After the duration of the reset interval, the watchdog timer starts  
a new 1.6 second timing interval; the microprocessor must service  
the watchdog input by changing states or by floating the WDI pin  
before this interval is finished. If the WDI pin is held either HIGH  
or LOW, a reset pulse will be triggered every 1.8 seconds (the 1.6  
second timing interval plus the reset pulse width tRS).  
(RESET)  
3.0V  
+5V  
+0V  
PFO  
VBATT = PFI = 3.0V  
IOUT = 0mA  
690A_04.eps  
( ) IMP805L  
Figure 2. Timing Diagram  
8
2
1
7
Battery-Switchover  
Circuit  
VBATT  
VCC  
VOUT  
Reset  
RESET  
Buffered RESET to Other System Components  
Generator  
(RESET)  
+
Watchdog  
Timer  
1.25V  
3.5V  
+
6
4
VCC  
VCC  
WDI  
PFI  
+
1.25V  
+
4.7k  
5
0.8V  
RESET  
RESET  
GND  
PFO  
IMP690A  
IMP690A, IMP692A, IMP802L, IMP802M,  
IMP805L  
GND  
3
690A_03.eps  
( ) IMP805L  
GND  
690A_05.eps  
Figure 3. Interfacing with bi-directional microprocessor  
reset inputs  
Figure 1. Block Diagram  
5
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中文翻译

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