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IMP5219CDWT

更新时间： 2024-02-03 19:04:20

品牌	Logo	应用领域
A1PROS		接口集成电路光电二极管信息通信管理
页数	文件大小	规格书
10页	299K
描述
9--Liine SCSII Termiinattor

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技术参数
数据手册

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IMP5219CDWT 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.68
Is Samacsys：	N	Base Number Matches：	1

IMP5219CDWT 数据手册

IMP51IM11P/55121129

DATA

OMMUNICATIONS

Key Features

9-Line SCSI Terminator

The 9-channel IMP5219 SCSI terminator is part of IMP's family of high-

performance SCSI terminators that deliver true UltraSCSI performance.

The BiCMOS design offers superior performance over first generation

linear regulator/ resistor based terminators.

ꢀ

Ultra-Fast response for Fast-20 SCSI applications

Hot swap compatible

35MHz channel bandwidth

IMP's new architecture employs high-speed adaptive elements for each

channel, thereby providing the fastest response possible - typically

35MHz, which is 100 times faster than the older linear regulator termi-

nator approach. The bandwidth of terminators based on the older

regulator/ resistor terminator architecture is limited to 500kHz since a

large output stabilization capacitor is required. The IMP architecture

eliminates the external output compensation capacitor and the need

for transient output capacitors while maintaining pin compatibility

with first generation designs. Reduced component count is inherent

with the IMP5219.

3.5V operation

Less than 3pF output capacitance

Sleep-mode current less than 375µA

Thermally self limiting

No external compensation capacitors

Implements 8-bit or 16-bit (wide) applications

Compatible with active negation drivers

(60ma/ channel)

ꢀ

Compatible with passive and active terminations

Approved for use with SCSI 1, 2, 3 and UltraSCSI

The IMP5219 architecture tolerates marginal system designs. A key

improvement offered by the IMP5219 lies in its ability to insure reliable,

error-free communications even in systems which do not adhere to rec-

ommended SCSI hardware design guidelines, such as improper cable

lengths and impedance. Frequently, this situation is not controlled by the

peripheral or host designer.

For portable and configurable peripherals, the IMP5219 can be placed in

a sleep mode with an active LOW disable signal. Quiescent current is

typically 375µA and output are in a high impedance state when disabled.

Block Diagrams

Term Power

24mA Current

Limiting Circuit

DATA OUTPUT

PIN DB (0)

Thermal

Limiting

Circuit

Current

Biasing

Circuit

2.85V

Disable Pin

–

1 of 9 Channels

1.4V

5219_01.eps

Data Communications

12 3 4 5 6 7...10

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