IMP5241/42/431
DATA
C
OMMUNICATIONS
Key Features
9-Line Multimode LVD/SE
SCSI Terminator
ꢀ Auto-selectable LVD or single-ended termination
ꢀ 3.0pF maximum disabled output capacitance
ꢀ Fast response, no external capacitors required
ꢀ Compatible with active negation drivers
ꢀ 15µA supply current in disconnect mode
ꢀ Logic command disconnects all termination lines
ꢀ DIFFSENSE line driver
The IMP5241/42/43 is a multimode SCSI terminator that conforms to the
SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10
standards committee for low voltage differential (LVD) termination,
while providing backwards compatibility to the SCSI, SCSI-2, and SPI
single-ended specifications. Multimode compatibility permits the use of
legacy devices on the bus without hardware alterations. Automatic mode
selection is achieved through voltage detection on the diffsense line.
ꢀ Ground driver integrated for single-ended
The IMP5241/42/43 delivers the ultimate in SCSI bus performance while
saving component cost and board area. Elimination of the external capac-
itors also mitigates the need for a lengthy capacitor selection process. The
individual high bandwidth drivers also maximize channel separation
and reduce channel to channel noise and cross talk. The high bandwidth
architecture insures ULTRA2 performance while providing a clear migra-
tion path to ULTRA3 and beyond.
operation
ꢀ Current limit and thermal protection
ꢀ Hot-swap compatible (single-ended)
ꢀ Compatible with SCSI 1, 2, 3, FAST-20, and the
pending SPI-2 LVD
ꢀ Pin compatible with DS2118, UCC5630 and
When the IMP5241/42/43 is enabled, the differential sense (DIFFSENSE)
pin supplies a voltage between 1.2V and 1.4V. In application, this pin is
LX5241/42/43
tied to the DIFFSENSE input of the corresponding LVD transceivers. This sleep/disable mode, power dissipation is reduced to a
action enables the LVD transceiver function. DIFFSENSE is capable of meager 15µA while also placing all outputs in a high
supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places impedance state. Also during sleep/disable mode, the
the IMP5241/42/43 in a high impedance state indicating the presence of DIFFSENSE function is disabled and is placed in a high
an HVD device. Tying the pin LOW places the part in a single-ended impedance state.
mode while also signaling the multimode transceiver to operate in a sin-
Another key feature of the IMP5241/42/43 is the mas-
gle-ended mode.
ter/slave function. Driving this pin HIGH or floating the
Recognizing the needs of portable and configurable peripherals, the pin enables the 1.3V DIFFSENSE reference. Driving the pin
IMP5241/42/43 have a TTL compatible sleep/disable mode. During this LOW disables the on board DIFFSENSE reference and
enables use of an external master reference device.
Block Diagram
1 of 9
SE 2.85V, 22.5mA
VTERM
Power ON
Internal VREF
1.30V
DISCONNECT
(IMP5241)
SE
2.2V
DISCONNECT
(IMP5242)
1.07mA
52.5
SE
LVD(-) / SE
DISC/HVD
200
LVD
1.25V
SE
LVD
HVD
LVD(+) / SE
52.5
(Pseudo-GND)
M/S
LVD
10mA
20
1.07mA
MODE Control & Delay
SE
Window
Comp.
Latch
HVD
DIFFSENSE
DIFF B
SE
HVD
LVD
20kΩ
LVD
Power ON & MODE Delay
Power ON
5241/42_01.eps
© 2001 IMP, Inc.
Data Communications
1
5秒后页面跳转
AO3401场效应管参数、引脚图、应用原理图
BT131可控硅参数及引脚图、工作原理详解
74LS32芯片参数、引脚图及功能真值表
全球首块英伟达H200交付 黄仁勋“送货上门”
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
