Datasheet > IMP16C554-LJ68

IMP16C554-LJ68

更新时间： 2024-02-27 03:29:25

品牌	Logo	应用领域
IMP		先进先出芯片
页数	文件大小	规格书
20页	493K
描述
Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs

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技术参数
数据手册

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IMP16C554-LJ68 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.7
Base Number Matches：	1

IMP16C554-LJ68 数据手册

IMP16C554

SYMBOL DESCRIPTION

symbol

TXRDY*

Signal

Type

Pin Description

Transmit ready. (active low) This pin goes high when the

transmit FIFO of the IMP16C554 is full. It can be used as a

single or multi-transfer.

Address select line 2.To select internal registers.

Address select line 1.To select internal registers.

Address select line 0.To select internal registers.

RXRDY*

Receive ready.(active low ) This pin goes low when the

receive FIFO is full. It can be used as a single or

multi-transfer.

INTSEL

Interrupt type select. Enable /disable the interrupt three state

function. Normal interrupt output can be selected by

connecting this pin to VCC(MCR bit-3 does not have any

effect on the interrupt output ).The three state interrupt output

is selected when this pin is left open or connected to GND

and MCR bit-3 is to “1”.

INT A-B

INT C-D

15.21

49.55

Interrupt output.( active high) this pin goes high (when enable

by the interrupt enable register)whenever a receiver error.

receiver data available. transmitter empty, or modem status

condition flag is detected.

RTS*A-B

RTS*C-D

14.22

48.56

Request to send.(active low) To indicate that the transmitter

has data ready to send .Writing a “1” in the modem control

reset this pin will be set to high. Note that this pin does not

have any effect on the transmit or receive operation.

DTR*A-B

DTR*C-D

12.24

46.58

Data terminal ready. (active low) To indicate that IMP16C554 is

ready to receive data. This pin can be controlled via the

modem control register (MCR bit-0).writing a “1” at the MCR

bit-0 will set the DTR* output to low.

408-432-9100/www.impweb.com

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