MATRA MHS
M 67025
Functional Description
The M 67025 has two ports with separate control, address if the CSs are low before an address match, on-chip
and I/0 pins that permit independent read/write access to control logic arbitrates between the left and right
any memory location. These devices have an automatic addresses for access (refer to table 4). The inhibited port’s
power-down feature controlled by CS.CS controls BUSY flag is set and will reset when the port granted
on-chip power-down circuitry which causes the port access completes its operation in both arbitration modes.
concerned to go into stand-by mode when not selected
(CS high). When a port is selected access to the full
memory array is permitted. Each port has its own Output
Data Bus Width Expansion
Enable control (OE). In read mode, the port’s OE turns the
Master/Slave Description
Output drivers on when set LOW. Non-conflicting
Expanding the data bus width to 32 or more bits in a
READ/WRITE conditions are illustrated in table 1.
dual-port RAM system means that several chips may be
The interrupt flag (INT) allows communication between
active simultaneously. If every chips has a hardware
ports or systems. If the user chooses to use the interrupt
arbitrator, and the addresses for each arrive at the same
function, a memory location (mail box or message center)
time one chip may activate in L BUSY signal while
is assigned to each port. The left port interrupt flag (INT )
L
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading
address location 1FFE. Similarly, the right port interrupt
To overcome this “Busy Lock-Out” problem, MHS has
developped a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to the
MASTER with no external components, giving a speed
advantage over other systems.
flag (INT ) is set when the left port writes to memory
R
location 1FFF (HEX), and the right port must read
memory location 1FFF in order to clear the interrupt flag
(INT ). The 16 bit message at 1FFE or 1FFF is
R
user-defined. If the interrupt function is not used, address
locations 1FFE and 1FFF are not reserved for mail boxes
but become part of the RAM. See table 3 for the interrupt
function.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until after
the BUSY input has settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation.
Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the
conflict is resolved. This timing is inherent in all
dual-port memory systems where more than one chip is
active at the same time.
Arbitration Logic
Functional Description
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns determine
which port has access. In all cases, an active BUSY flag
will be set for the inhibited port.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
The BUSY flags are required when both ports attempt to
access the same location simultaneously. Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the Semaphore Logic
inhibited port. BUSY is set at speeds that allow the
Functional Description
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
The M 67025 is an extremely fast dual-port 4k × 16
CMOS static RAM with an additional locations dedicated
to binary semaphore flags. These flags allow either of the
A conflict will occur when both left and right ports are processors on the left or right side of the dual-port RAM
active and the two addresses coincide. The on-chip to claim priority over the other for functions defined by
arbitration determines access in these circumstances. the system software. For example, the semaphore flag can
Two modes of arbitration are provided : (1) if the be used by oner processor to inhibit the other from
addresses match and are valid before CS on-chip control accessing a portion of the dual-port RAM or any other
logic arbitrates between CS and CS for access ; or (2) shared resource.
L
R
Rev. D (29/09/95)
5
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