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IDT82V3155PV8 PDF预览

IDT82V3155PV8

更新时间: 2024-02-16 07:51:45
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
30页 388K
描述
PLL Based Clock Driver, 7 True Output(s), 5 Inverted Output(s), PDSO56, SSOP-56

IDT82V3155PV8 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP-56针数:56
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.91Is Samacsys:N
输入调节:STANDARDJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:18.415 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:5
端子数量:56实输出次数:7
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.5 mm
Base Number Matches:1

IDT82V3155PV8 数据手册

 浏览型号IDT82V3155PV8的Datasheet PDF文件第1页浏览型号IDT82V3155PV8的Datasheet PDF文件第2页浏览型号IDT82V3155PV8的Datasheet PDF文件第3页浏览型号IDT82V3155PV8的Datasheet PDF文件第5页浏览型号IDT82V3155PV8的Datasheet PDF文件第6页浏览型号IDT82V3155PV8的Datasheet PDF文件第7页 
IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS  
INDUSTRIAL TEMPERATURE  
LIST OF FIGURES  
Figure - 1  
Figure - 2  
Figure - 3  
Figure - 4  
Figure - 5  
Figure - 6  
Figure - 7  
Figure - 8  
Figure - 9  
IDT82V3155 SSOP56 Package Pin Assignment ................................................................................................................................ 2  
State Control Circuit ............................................................................................................................................................................ 9  
State Control Diagram......................................................................................................................................................................... 9  
TIE Control Block Diagram................................................................................................................................................................ 11  
Reference Switch with TIE Control Block Enabled............................................................................................................................ 12  
Reference Switch with TIE Control Block Disabled........................................................................................................................... 12  
DPLL Block Diagram......................................................................................................................................................................... 13  
Clock Oscillator Circuit ...................................................................................................................................................................... 14  
Power-Up Reset Circuit..................................................................................................................................................................... 14  
Figure - 10 Timing Parameter Measurement Voltage Levels .............................................................................................................................. 25  
Figure - 11 Input to Output Timing (Normal Mode).............................................................................................................................................. 27  
Figure - 12 Output Timing 1................................................................................................................................................................................. 28  
Figure - 13 Output Timing 2................................................................................................................................................................................. 29  
Figure - 14 Input Control Setup and Hold Timing ................................................................................................................................................ 29  
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