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IDT821068PX PDF预览

IDT821068PX

更新时间: 2024-01-27 03:18:06
品牌 Logo 应用领域
艾迪悌 - IDT 解码器编解码器PC
页数 文件大小 规格书
45页 567K
描述
OCTAL PROGRAMMABLE PCM CODEC

IDT821068PX 数据手册

 浏览型号IDT821068PX的Datasheet PDF文件第36页浏览型号IDT821068PX的Datasheet PDF文件第37页浏览型号IDT821068PX的Datasheet PDF文件第38页浏览型号IDT821068PX的Datasheet PDF文件第40页浏览型号IDT821068PX的Datasheet PDF文件第41页浏览型号IDT821068PX的Datasheet PDF文件第42页 
IDT821068 OCTAL PROGRAMMABLE PCM CODEC  
INDUSTRIAL TEMPERATURE RANGE  
PCM Interface  
Parameter  
t51  
Description  
Data enable delay time  
Min  
5
Typ  
Max  
70  
Units  
ns  
Test Conditions  
t52  
t53  
Data delay time from BCLK  
Data float delay time  
5
5
70  
70  
ns  
ns  
t54  
t55  
t56  
t57  
Frame sync setup time  
Frame sync hold time  
25  
50  
5
t4 - 50  
ns  
ns  
ns  
ns  
TSX  
TSX  
80  
80  
enable delay time  
5
disable delay time  
t61  
t62  
Receive data setup time  
Receive data hold time  
25  
5
ns  
ns  
Time Slot  
BCLK  
1
2
3
4
5
6
7
8
1
t54  
t55  
FS  
t53  
t52  
t51  
DX1/  
DX2  
BIT 1  
BIT 2  
t61  
BIT 3  
BIT 4  
BIT 5  
BIT 6  
BIT 7  
BIT 8  
t62  
DR1/  
DR2  
BIT  
1
BIT  
2
BIT  
3
BIT  
4
BIT  
5
BIT  
6
BIT  
7
BIT  
8
t56  
t57  
TSX1  
/
TSX2  
Figure 16. Transmit and Receive Timing *  
Note*: These timing diagram only apply to the situation when data clock in on falling edges and clock out on rising edges.  
Time Slot  
27 28 29 30 31  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26  
FS  
DX  
X0  
X1  
X2  
X3  
DR  
R0  
R1  
R2  
R3  
TSX  
Figure 17. Typical Frame Sync Timing (2 MHz Operation)  
39  

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