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IDT821054PQFG PDF预览

IDT821054PQFG

更新时间: 2024-01-23 01:02:52
品牌 Logo 应用领域
艾迪悌 - IDT 解码器编解码器电信集成电路电信电路PC
页数 文件大小 规格书
45页 495K
描述
PCM Codec, A/MU-Law, 1-Func, PQFP64, PLASTIC, QFP-64

IDT821054PQFG 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:PLASTIC, QFP-64针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83压伸定律:A/MU-LAW
滤波器:YESJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:14 mm
功能数量:1端子数量:64
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:2.45 mm标称供电电压:5 V
表面贴装:YES电信集成电路类型:PROGRAMMABLE CODEC
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:14 mm

IDT821054PQFG 数据手册

 浏览型号IDT821054PQFG的Datasheet PDF文件第6页浏览型号IDT821054PQFG的Datasheet PDF文件第7页浏览型号IDT821054PQFG的Datasheet PDF文件第8页浏览型号IDT821054PQFG的Datasheet PDF文件第10页浏览型号IDT821054PQFG的Datasheet PDF文件第11页浏览型号IDT821054PQFG的Datasheet PDF文件第12页 
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE  
INDUSTRIAL TEMPERATURE RANGE  
interface and the Coefficient-RAM of the IDT821054 are programmed by  
the master device via MPI, which consists of four lines (pins): CCLK, CS,  
CI and CO. All commands and data are aligned in byte (8 bits) and  
transferred via the MPI interface. CCLK is the clock of the MPI interface.  
The frequency of CCLK can be up to 8.192 MHz. CS is the chip  
selection pin. A low level on CS enables the MPI interface. CI and CO  
are data input and data output pins, carrying control commands and  
data bytes to/from the IDT821054.  
2
FUNCTIONAL DESCRIPTION  
The IDT821054 is a four-channel PCM CODEC with on-chip digital  
filters. It provides a four-wire solution for the subscriber line circuitry in  
digital switches. The IDT821054 converts analog voice signals to digital  
PCM samples and digital PCM samples back to analog voice signals.  
The digital filters are used to bandlimit the voice signals during  
conversion. High performance oversampling Analog-to-Digital  
Converters (ADC) and Digital-to-Analog Converters (DAC) in the  
IDT821054 provide the required conversion accuracy. The associated  
decimation and interpolation filtering is performed by both dedicated  
hardware and Digital Signal Processor (DSP). The DSP also handles all  
other necessary procession such as PCM bandpass filtering, sample  
rate conversion and PCM companding.  
The data transfer is synchronized to the CCLK signal. The contents  
of CI is latched on the rising edges of CCLK, while CO changes on the  
falling edges of CCLK. The CCLK signal is the only reference of CI and  
CO pins. Its duty and frequency may not necessarily be standard.  
When the CS pin becomes low, the IDT821054 treats the first byte on  
the CI pin as command and the rest as data. To write another command,  
the CS pin must be changed from low to high to finish the previous  
command and then changed from high to low to indicate the start of a  
new command. When a read/write operation is completed, the CS pin  
must be set to high in 8-bit time.  
2.1  
MPI/PCM INTERFACE  
A serial Microprocessor Interface (MPI) is provided for the master  
device to control the IDT821054. Two PCM buses are provided to  
transfer the digital voice data.  
During the execution of commands that are followed by output data  
byte(s), the IDT821054 will not accept any new commands from the CI  
pin. But the data transfer sequence can be interrupted by setting the CS  
pin to high at any time. See Figure - 1 and Figure - 2 for examples of  
MPI write and read operation timing diagrams.  
2.1.1  
MICROPROCESSOR INTERFACE (MPI)  
The internal configuration registers (local/global), the SLIC signaling  
CCLK  
CS  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CI  
Command Byte  
Data Byte 1  
Data Byte 2  
High 'Z'  
CO  
Figure - 1 An Example of the MPI Interface Write Operation  
CCLK  
CS  
Ignored  
7
6
5
4
3
2
1
0
CI  
Command Byte  
Identification Code  
Data Byte 1  
High 'Z'  
CO  
'1' '0' '0' '0' '0' '0' '0' '1'  
7
6
5
4
3
2
1
0
Figure - 2 An Example of the MPI Interface Read Operation (ID = 81H)  
9

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