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IDT821054PQFG PDF预览

IDT821054PQFG

更新时间: 2024-02-02 07:47:16
品牌 Logo 应用领域
艾迪悌 - IDT 解码器编解码器电信集成电路电信电路PC
页数 文件大小 规格书
45页 495K
描述
PCM Codec, A/MU-Law, 1-Func, PQFP64, PLASTIC, QFP-64

IDT821054PQFG 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:PLASTIC, QFP-64针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83压伸定律:A/MU-LAW
滤波器:YESJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:14 mm
功能数量:1端子数量:64
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:2.45 mm标称供电电压:5 V
表面贴装:YES电信集成电路类型:PROGRAMMABLE CODEC
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:14 mm

IDT821054PQFG 数据手册

 浏览型号IDT821054PQFG的Datasheet PDF文件第5页浏览型号IDT821054PQFG的Datasheet PDF文件第6页浏览型号IDT821054PQFG的Datasheet PDF文件第7页浏览型号IDT821054PQFG的Datasheet PDF文件第9页浏览型号IDT821054PQFG的Datasheet PDF文件第10页浏览型号IDT821054PQFG的Datasheet PDF文件第11页 
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE  
INDUSTRIAL TEMPERATURE RANGE  
Name  
Type  
Pin Number  
Description  
Chip Selection.  
CS  
I
17  
A logic low level on this pin enables the Serial Control Interface.  
Serial Control Interface Data Input.  
CI  
CO  
I
O
I
19  
20  
18  
Control data input pin. CCLK determines the data rate.  
Serial Control Interface Data Output (Tri-State).  
Control data output pin. CCLK determines the data rate.  
Serial Control Interface Clock.  
CCLK  
This is the clock for the Serial Control Interface. It can be up to 8.192 MHz.  
Master Clock Input.  
MCLK  
RESET  
INT12  
I
I
22  
23  
34  
This pin provides the clock for the DSP of the IDT821054. The frequency of the MCLK can be 1.536 MHz,  
1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz.  
Reset Input.  
Forces the device to default mode. Active low.  
Interrupt Output Pin for Channel 1-2.  
O
Active high interrupt signal for Channel 1 and 2, open-drain. It reflects the changes on the corresponding  
SLIC input pins.  
Interrupt Output Pin for Channel 3-4.  
INT34  
O
15  
Active high interrupt signal for Channel 3 and 4, open-drain. It reflects the changes on the corresponding  
SLIC input pins.  
Chopper Clock Output One.  
CHCLK1  
CHCLK2  
O
O
33  
16  
Provides a programmable output signal (2 -28 ms) synchronous to MCLK.  
Chopper Clock Output Two.  
Provides a programmable output signal (256 kHz, 512 kHz or 16.384 MHz) synchronous to MCLK.  
8

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