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IDT79RV3041-25PF PDF预览

IDT79RV3041-25PF

更新时间: 2024-01-18 23:55:29
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
34页 392K
描述
RISC Microprocessor, 32-Bit, 25MHz, CMOS, PQFP100, CAVITY UP, TQFP-100

IDT79RV3041-25PF 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP100,.63SQ,20
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.87Is Samacsys:N
其他特性:BURST BUS; 5 PIPELINE STAGES地址总线宽度:32
位大小:32边界扫描:NO
最大时钟频率:50 MHz外部数据总线宽度:32
格式:FIXED POINT集成缓存:NO
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm低功率模式:NO
湿度敏感等级:3DMA 通道数量:
外部中断装置数量:6串行 I/O 数:
端子数量:100片上数据RAM宽度:
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH电源:3.3 V
认证状态:Not QualifiedRAM(字数):0
座面最大高度:1.6 mm速度:25 MHz
子类别:Microprocessors最大压摆率:180 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

IDT79RV3041-25PF 数据手册

 浏览型号IDT79RV3041-25PF的Datasheet PDF文件第1页浏览型号IDT79RV3041-25PF的Datasheet PDF文件第2页浏览型号IDT79RV3041-25PF的Datasheet PDF文件第4页浏览型号IDT79RV3041-25PF的Datasheet PDF文件第5页浏览型号IDT79RV3041-25PF的Datasheet PDF文件第6页浏览型号IDT79RV3041-25PF的Datasheet PDF文件第7页 
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS  
COMMERCIAL TEMPERATURE RANGE  
System Control Co-Processor  
dress decoding, or in other system specific forms. In systems  
which do not wish to implement memory protection, and wish  
to have the kernel and user tasks operate out of a single  
unified memory space, upper address lines can be ignored by  
the address decoder, and thus all references will be seen in  
the lower gigabyte of the physical address space.  
TheR3041addsadditionalresourcesintotheon-chipCP0.  
These resources are detailed in the R3041 User's Manual.  
They allow kernel software to directly control activity of the  
processor internal resources and bus interface, and include:  
Cache Configuration Register: This register controls the  
data cache block size and miss refill algorithm.  
Bus Control Register: This register controls the behavior  
of the various bus interface signals.  
Count and Compare Registers: Together, these two  
registers implement a programmable 24-bit timer, which  
can be used for DRAM refresh or as a general purpose  
timer.  
The R3041 also integrates on-chip a System Control Co-  
processor, CP0. CP0 manages the exception handling capa-  
bility of the R3041, the virtual to physical address mapping of  
the R3041, and the programmable bus interface capabilities  
of the R3041. These topics are discussed in subsequent  
sections.  
TheR3041doesnotincludetheoptionalTLBfoundinother  
membersoftheRISControllerfamily,butinsteadperformsthe  
same virtual to physical address mapping of the base version  
of the RISController family. These devices still support  
distinct kernel and user mode operation, but do not require  
page management software or an on-chip TLB, leading to a  
simpler software model and a lower-cost processor.  
The memory mapping used by these devices is illustrated  
in Figure 3. Note that the reserved address spaces shown are  
for compatibility with future family members; in the current  
family members, references to these addresses are trans-  
lated in the same fashion as their respective segments, with  
no traps or exceptions taken.  
PortSizeControlRegister: Thisregisterallowsthekernel  
to indicate the port width of reads and writes to various sub-  
regionsofthephysicaladdressspace. Thus,theR3041can  
interface directly with 8-, 16-, and 32-bit memory ports,  
including a mix of sizes, for both instruction and data  
references, without requiring additional external logic.  
When using the base versions of the architecture, the  
system designer can implement a distinction between the  
user tasks and the kernel tasks, without having to execute  
page management software. This distinction can take the  
form of physical memory protection, accomplished by ad-  
PHYSICAL  
VIRTUAL  
0xffffffff  
0xffffffff  
Kernel Reserved  
1MB  
Kernel Reserved  
0xfff00000  
0xffefffff  
1MB  
0xfff00000  
0xffefffff  
Kernel Cached  
Tasks  
Kernel Cached  
(kseg2)  
1023 MB  
0xc0000000  
0xbfffffff  
0xc0000000  
0xbfffffff  
User Reserved  
1MB  
Kernel Uncached  
(kseg1)  
0xbff00000  
0xbfefffff  
0xa0000000  
0x9fffffff  
Kernel Cached  
(kseg0)  
Kernel/User  
Cached  
0x80000000  
0x7fffffff  
0x7ff00000  
0x7fefffff  
Tasks  
User Reserved  
1MB  
2047 MB  
Kernel/User  
Cached  
0x40000000  
0x3fffffff  
Inaccessible  
512 MB  
(kuseg)  
0x20000000  
0x1fffffff  
Kernel Boot  
and I/O  
0x00000000  
0x00000000  
512 MB  
2905 drw 03  
Figure 3. Virtual to Physical Mapping of Base Architecture Versions  
3

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