IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The extended architecture versions of the R3051 family
(theR3051E,R3052E,andR3081E)allowthesystemdesigner
to implement kernel software which dynamically manages
user task utilization of system resources, and also allows the
Kernel to protect certain resources from user tasks. These
capabilities are important in general computing applications
such as ARC computers, and are also important in a variety of
embeddedapplications,fromprocesscontrol(whereprotection
may be important) to X-Window display systems (where
virtual memory management can be used). The MMU can
also be used to simplify system debug.
I#1
IF
RD ALU MEM WB
I#2
IF
RD ALU MEM WB
I#3
IF
RD ALU MEM WB
I#4
IF
RD ALU MEM WB
I#5
IF
RD ALU MEM WB
R3051familybaseversions(theR3051,R3052,andR3081)
remove the TLB and institute a fixed address mapping for the
varioussegmentsofthevirtualaddressspace. Thesedevices
still support distinct kernel and user mode operation, but do
not require page management software, leading to a simpler
software model. The memory mapping used by these devices
is shown in Figure 4. Note that the reserved spaces are for
compatiblity with future family members, which may map on-
chip resources to these addresses. References to these
addresses in the R3081 will be translated in the same fashion
as the rest of their respective segments, with no traps or
exceptions signalled.
When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to implement
page management software. This distinction can be
implemented by decoding the output physical address. In
systems which do not need memory protection, and wish to
have the kernel and user tasks operate out of the same
memory space, high-order address lines can be ignored by
the address decoder, and thus all references will be seen in
the lower gigabyte of the physical address space.
Current
CPU
Cycle
2889 drw 02
Figure 2. R3081 5-Stage Pipeline
VIRTUAL
PHYSICAL
0xffffffff
0xc0000000
Kernel Mapped
(kseg2)
Any
Kernel Uncached
(kseg1)
Physical
Memory
3548MB
0xa0000000
0x80000000
Kernel Cached
(kseg0)
User Mapped
Cacheable
(kuseg)
Any
Floating Point Co-Processor
Memory
The R3081 also integrates an R3010A compatible floating
point accelerator on-chip. The FPA is a high-performance co-
processor (co-processor 1 to the CPU) providing separate
add, multiply, and divide functional units for single and double
precisionfloatingpointarithmetic.Thefloatingpointaccelerator
features low latency operations, and autonomous functional
units which allow differing types of floating point operations to
function concurrently with integer operations. The R3010A
appears to the software programmer as a simple extension of
the integer execution unit, with 16 dedicated 64-bit floating
pointregisters(softwarereferencestheseas3232-bitregisters
when performing loads or stores). Figure 5 illustrates the
functional block diagram of the on-chip FPA.
512 MB
0x00000000
2889 drw 03
Figure 3. Virtual to Physical Mapping of Extended Architecture
Versions
VIRTUAL
PHYSICAL
0xffffffff
0xc0000000
1MB Kernel Rsvd
Kernel Cacheable
Tasks
Kernel Cached
(kseg2)
1024 MB
Kernel Uncached
(kseg1)
0xa0000000
0x80000000
Kernel/User
Cacheable
Tasks
Kernel Cached
(kseg0)
2048 MB
512 MB
Clock Generator Unit
The R3081 is driven from a single input clock which can be
eitherattheprocessorratedspeed, orattwicethatspeed. On-
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
R3081 includes an on-chip clock doubler to provide higher
frequency signals to the internal execution core; if 1x clock
mode is selected, the clock doubler will internally convert it to
1MB User Rsvd
User
Cached
(kuseg)
Inaccessible
Kernel Boot
and I/O
512 MB
2889 drw 04
0x00000000
Figure 4. Virtual to Physical Mapping of Base Architecture Versions
5.5
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