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IDT7383L45GB PDF预览

IDT7383L45GB

更新时间: 2024-10-02 21:06:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟输入元件外围集成电路
页数 文件大小 规格书
7页 72K
描述
Bit-Slice Processor, 16-Bit, CMOS, CPGA68, CAVITY-UP, PGA-68

IDT7383L45GB 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:PGA包装说明:CAVITY-UP, PGA-68
针数:68Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.31.00.01
风险等级:5.9Is Samacsys:N
其他特性:2 X 16 BIT DATA INPUT BUS; 5 CONTROL PINS TO SELECT OPERATION; ICC SPECIFIED @ 10MHZ最大时钟频率:26.31 MHz
外部数据总线宽度:16JESD-30 代码:S-CPGA-P68
JESD-609代码:e0长度:29.464 mm
端子数量:68最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:5.207 mm
最大压摆率:90 mA最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:29.464 mmuPs/uCs/外围集成电路类型:BIT-SLICE MICROPROCESSOR
Base Number Matches:1

IDT7383L45GB 数据手册

 浏览型号IDT7383L45GB的Datasheet PDF文件第2页浏览型号IDT7383L45GB的Datasheet PDF文件第3页浏览型号IDT7383L45GB的Datasheet PDF文件第4页浏览型号IDT7383L45GB的Datasheet PDF文件第5页浏览型号IDT7383L45GB的Datasheet PDF文件第6页浏览型号IDT7383L45GB的Datasheet PDF文件第7页 
IDT7014S  
HIGH-SPEED  
4K x 9 DUAL-PORT  
STATIC RAM  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
• High-speed access  
The IDT7014 is an extremely high-speed 4K x 9 Dual-Port  
Static RAM designed to be used in systems where on-chip  
hardware port arbitration is not needed. This part lends itself  
to high-speed applications which do not need on-chip arbitra-  
tion to manage simultaneous access.  
— Military: 20/25/35ns (max.)  
— Commercial: 12/15/20/25ns (max.)  
• Low-power operation  
The IDT7014 provides two independent ports with separate  
control, address, and I/O pins that permit independent,  
asynchronous access for reads or writes to any location in  
memory. See functional description.  
The IDT7014 utilitizes a 9-bit wide data path to allow for  
parity at the user's option. This feature is especially useful in  
data communication applications where it is necessary to use  
a parity bit for transmission/reception error checking.  
Fabricated using IDT’s high-performance technology, the  
IDT7014 Dual-Ports typically operate on only 900mW of  
power at maximum access times as fast as 12ns.  
— IDT7014S  
Active: 900mW (typ.)  
• Fully asynchronous operation from either port  
• TTL-compatible; single 5V (±10%) power supply  
• Available in 52-pin PLCC and a 64-pin TQFP  
• Industrial temperature range (–40°C to +85°C) is avail-  
able, tested to military electrical specifications  
The IDT7014 is packaged in a 52-pin PLCC and a 64-pin  
thin plastic quad flatpack (TQFP).  
FUNCTIONAL BLOCK DIAGRAM  
R/W  
L
R/WR  
OEL  
OER  
COLUMN  
CONTROL  
COLUMN  
CONTROL  
I/O0L- I/O8L  
I/O0R- I/O8R  
LEFT SIDE  
ADDRESS  
DECODE  
LOGIC  
RIGHT SIDE  
ADDRESS  
DECODE  
LOGIC  
MEMORY  
ARRAY  
A
0L- A11L  
A0R- A11R  
2528 drw 01  
The IDT logo is a registereed trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
OCTOBER 1996  
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.  
©1996 Integrated Device Technology, Inc.  
DSC-2528/6  
6.11  
1

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