IDT74FCT162H501AT/CT
FASTCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
FAST CMOS
IDT54/74FCT162H501AT/CT
18-BIT REGISTERED
TRANSCEIVER
DESCRIPTION:
FEATURES:
TheFCT162H501T18-bitregisteredtransceiversarebuiltusingadvanced
dualmetalCMOStechnology.Thesehigh-speed,low-power18-bitregistered
bustransceiverscombineD-typelatchesandD-typeflip-flopstoallowdataflow
in transparent, latched and clocked modes. Data flow in each direction is
controlledbyoutput-enable(OEABandOEBA),latchenable(LEABandLEBA)
andclock(CLKABandCLKBA)inputs.ForA-to-Bdataflow,thedeviceoperates
intransparentmodewhenLEABishigh.WhenLEABislow,theAdataislatched
if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is
storedinthelatch/flip-floponthelow-to-hightransitionofCLKAB.OEABis the
outputenablefortheBport.DataflowfromtheBporttotheAportissimilarbut
requiresusing OEBA,LEBAandCLKBA.Flow-throughorganizationofsignal
pinssimplifieslayout.Allinputsaredesignedwithhysteresisforimprovednoise
margin.
• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤ 1µA (max.)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull up resistors
• Available in SSOP and TSSOP packages
The FCT162H501T has "Bus Hold" which retains the input's last state
whenevertheinputgoestohighimpedance. Thisprevents"floating"inputsand
eliminatestheneedforpull-up/downresistors.
FUNCTIONALBLOCKDIAGRAM
1
OEAB
30
CLKBA
28
LEBA
27
OEBA
55
CLKAB
2
LEAB
C
C
54
B1
3
A1
D
D
C
D
C
D
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5434/1