3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT72V8985
andwriteaccesstoindividualchannels. Asanimportantfunctionofadigital
switchis tomaintainsequenceintegrityandminimizethroughputdelay, the
IDT72V8985isanidealsolutionformostswitchingneeds.
FEATURES:
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256 x 256 channel non-blocking switch
Automatic signal identification (ST-BUS®, GCI)
8 RX inputs—32 channels at 64 Kbit/s per serial line
8 TX outputs—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
Frame Integrity for data applications
3.3V Power Supply
FUNCTIONALDESCRIPTION
Framesequence,constantthroughputdelay,andguaranteedminimum
delayarehighpriorityrequirementsintoday’sintegrateddataandmultimedia
networks. TheIDT72V8985providesthesefunctionsonaper-channelbasis
usingastandardmicroprocessorcontrolinterface. Eachoftheeightseriallines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
InProcessorMode,themicroprocessorcanaccesstheinputandoutputtime
slotstocontrolotherdevicessuchasISDNtransceiversandtrunkinterfaces.
SupportingbothGCIandST-BUS® formats,IDT72V8985hasincorporatedan
internal circuit to automatically identify the polarity and format of the frame
synchronization.
Available in 44-pin Plastic Leaded Chip Carrier (PLCC),
48-pin Small Shrink Outline Package (SSOP), and 44-pin Plastic
Quad Flatpack (PQFP)
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Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V Tolerant Inputs
AfunctionalblockdiagramoftheIDT72V8985deviceisshownonpage1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µswideframeseachcontaining32,8-bitchannels. Eightinput(RX0-7)and
eight output (TX0-7) serial streams are provided in the IDT72V8985 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. Theserialinterfaceclockforthedeviceis 4.096MHz.
DESCRIPTION:
TheIDT72V8985isaST-BUS®/GCIcompatibledigitalswitchcontrolledby
amicroprocessor. TheIDT72V8985canhandleasmanyas256,64Kbit/sinput
andoutputchannels. Those256channelsaredividedinto8serialinputsand
outputs,eachofwhichconsistsof32channels.TheIDT72V8985providesper-
channelvariableorconstantthroughputdelaymodesandmicroprocessorread
FUNCTIONAL BLOCK DIAGRAM
RESET(1)
ODE
C4i F0i
VCC GND
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
Timing
Unit
RX0
Output MUX
RX1
RX2
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
RX3
Data
Memory
RX4
RX5
RX6
RX7
Connection
Memory
Control Register
Microprocessor Interface
5707 drw01
CCO
DS
A0/
A5
CS
R/W
D0/
D7
DTA
NOTE:
1. The RESET Input is only provided on the SSOP package.
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS isatrademarkofMitelCorp.
AUGUST 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5707/5