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IDT72V831L10TF PDF预览

IDT72V831L10TF

更新时间： 2024-02-22 23:01:41
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 152K
描述
3.3 VOLT DUAL CMOS SyncFIFO⑩

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IDT72V831L10TF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：GREEN, PLASTIC, STQFP-64针数：64
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.5
最长访问时间：6.5 ns最大时钟频率 (fCLK)：100 MHz
周期时间：10 nsJESD-30 代码：S-PQFP-G64
JESD-609代码：e3长度：10 mm
内存密度：18432 bit内存集成电路类型：BI-DIRECTIONAL FIFO
内存宽度：9湿度敏感等级：3
功能数量：1端子数量：64
字数：2048 words字数代码：2000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2KX9
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP64,.47SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.01 A
子类别：FIFOs最大压摆率：0.04 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：10 mm
Base Number Matches：1

IDT72V831L10TF 数据手册

 浏览型号IDT72V831L10TF的Datasheet PDF文件第1页浏览型号IDT72V831L10TF的Datasheet PDF文件第2页浏览型号IDT72V831L10TF的Datasheet PDF文件第4页浏览型号IDT72V831L10TF的Datasheet PDF文件第5页浏览型号IDT72V831L10TF的Datasheet PDF文件第6页浏览型号IDT72V831L10TF的Datasheet PDF文件第7页 
IDT72V801/72V811/72V821/72V831/72V841/72V851  
COMMERCIALANDINDUSTRIALTEMPERATURERANGE  
PINDESCRIPTIONS  
TheIDT72V801/72V811/72V821/72V831/72V841/72V851'stwoFIFOs,  
referredtoasFIFOAandFIFOB,areidenticalineveryrespect.Thefollowing  
descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorresponding  
signal names for FIFO B are provided in parentheses.  
Symbol  
DA0-DA8  
DB0-DB8  
RSA, RSB  
Name I/O  
ADataInputs  
BDataInputs  
Reset  
Description  
I
I
I
9-bit data inputs to RAM array A.  
9-bit data inputs to RAM array B.  
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first  
location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-  
up, a reset of both FIFOs A and B is required before an initial WRITE.  
WCLKA  
WCLKB  
Write Clock  
I
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s)  
areasserted.  
WENA1  
WENB1  
WriteEnable1  
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be  
used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition  
WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and  
WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is  
LOW.  
WENA2/LDA  
WENB2/LDB  
WriteEnable2/  
Load  
I
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at  
reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates  
as a controltoloadandreadthe programmable flagoffsets forits respective array. Ifthe FIFOis configuredtohave  
two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO  
A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable  
flags, LDA(LDB)is heldLOWtowrite orreadthe programmable flagoffsets.  
QA0-QA8  
QB0-QB8  
ADataOutputs  
BDataOutputs  
Read Clock  
O
O
I
9-bitdata outputs fromRAMarrayA.  
9-bitdata outputs fromRAMarrayB.  
RCLKA  
RCLKB  
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and  
RENA2 (RENB2) are asserted.  
RENA1  
RENB1  
ReadEnable1  
ReadEnable2  
OutputEnable  
Empty Flag  
I
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH  
transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.  
RENA2  
RENB2  
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-  
HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.  
OEA  
I
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0-  
DA8 (DB0-DB8)willbe ina high-impedance state.  
EFA  
EFB  
O
O
O
O
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA  
(EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).  
PAEA  
PAEB  
Programmable  
Almost-EmptyFlag  
When PAEA (PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate  
offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB).  
PAFA  
PAFB  
Programmable  
Almost-FullFlag  
When PAFA(PAFB)is LOW, FIFOA(B)is Almost-Fullbasedonthe offsetprogrammedintothe appropriate offset  
register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).  
FFA  
FFB  
FullFlag  
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is  
HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).  
VCC  
Power  
Ground  
+3.3V power supply pin.  
0V groundpin.  
GND  
3
1234567...16

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