IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
When either of the two Read Enable, RENA1, RENA2 (RENB1, RENB2)
associatedwithFIFOA(B)isHIGH,theoutputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
When all the data has been read from FIFO A (B), the Empty Flag, EFA
(EFB) will go LOW, inhibiting further read operations. Once a valid write
operationhas beenaccomplished, EFA (EFB)willgoHIGHaftertREF anda
valid read can begin. The Read Enables, RENA1, RENA2(RENB1, RENB2)
are ignored when FIFO A (B) is empty.
SIGNALDESCRIPTIONS
FIFOAandFIFOBareidenticalineveryrespect.Thefollowingdescription
explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8) — DA0 - DA8 are the nine data inputs
formemoryarrayA. DB0 -DB8 are the nine data inputs formemoryarrayB.
Output Enable (OEA, OEB) — When Output Enable, OEA (OEB) is
enabled(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheir
respective output register. When Output Enable, OEA (OEB) is disabled
(HIGH), the QA(QB)outputdata bus is ina high-impedance state.
CONTROLS:
Reset(RSA,RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA
(RSB)inputistakentoaLOWstate.Duringreset,theinternalreadandwrite
pointersassociatedwiththeFIFOaresettothefirstlocation.Aresetisrequired
after power-up before a write operation can take place. The Full Flag, FFA
(FFB)andProgrammableAlmost-FullFlag,PAFA(PAFB)willberesettoHIGH
aftertRSF. TheEmptyFlag,EFA(EFB)andProgrammableAlmost-EmptyFlag,
PAEA(PAEB)willberesettoLOWaftertRSF. Duringreset,theoutputregister
isinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefault
values.
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual-
purposepin. FIFOA(B)isconfiguredatResettohaveprogrammableflags
ortohavetwowriteenables,whichallowsdepthexpansion. IfWENA2/LDA
(WENB2/LDB) issetHIGHatReset,RSA=LOW(RSB=LOW),thispinoperates
as a secondWrite Enable pin.
IfFIFOA(B)isconfiguredtohavetwowriteenables,whenWriteEnable
1,WENA1(WENB1)isLOWandWENA2/LDA(WENB2/LDB)isHIGH,datacan
beloadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition
ofeveryWriteClock,WCLKA(WCLKB). Dataisstoredinthearraysequentially
and independently of any on-going read operation.
Inthisconfiguration,whenWENA1(WENB1)isHIGHand/orWENA2/LDA
(WENB2/LDB)is LOW,the inputregisterofArrayAholds the previous data
and no new data is allowed to be loaded into the register.
Topreventdataoverflow,theFullFlag,FFA(FFB)willgoLOW,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,FFA(FFB)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WENA1,(WENB1)and
WENA2/LDA (WENB2/LDB)are ignoredwhenthe FIFOis full.
WriteClock(WCLKA,WCLKB)—AwritecycletoArrayA(B)isinitiated
ontheLOW-to-HIGHtransitionofWCLKA(WCLKB). Dataset-upandhold
times must be met with respect to the LOW-to-HIGH transition of WCLKA
(WCLKB). The Full Flag, FFA (FFB) and Programmable Almost-Full Flag,
PAFA(PAFB)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionof
theWriteClock,WCLKA(WCLKB).
The Write and Read clock can be asynchronous or coincident.
Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for
programmable flags,WENA1(WENB1)is theonlyenablecontrolpin.Inthis
configuration,whenWENA1(WENB1)isLOW,datacanbeloadedintotheinput
register of RAM Array A (B) on the LOW-to-HIGH transition of every Write
Clock, WCLKA (WCLKB). Data is stored in Array A (B) sequentially and
independently of any on-going read operation.
FIFOA(B)isconfiguredtohaveprogrammableflagswhentheWENA2/
LDA(WENB2/LDB)issetLOWatReset,RSA = LOW(RSB = LOW). EachFIFO
In this configuration, when WENA1 (WENB1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the
register.
IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
Topreventdataoverflow,FFA(FFB)willgoLOW,inhibitingfurtherwrite
operations. Uponthecompletionofavalidreadcycle,theFFA(FFB)willgo
HIGHaftertWFF,allowingavalidwritetobegin. WENA1(WENB1)isignored
when FIFO A (B) is full.
LDA
LDB
0
WENA1
WENB1
0
WCLKA
WCLKB
OPERATION ON FIFO A
OPERATION ON FIFO B
Empty Offset (LSB)
Empty Offset (MSB)
FullOffset(LSB)
Full Offset (MSB)
0
1
1
0
1
NoOperation
WriteIntoFIFO
NoOperation
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B)
onthe LOW-to-HIGHtransitionofRCLKA(RCLKB). The EmptyFlag, EFA
(EFB)andProgrammableAlmost-EmptyFlag,PAEA(PAEB)aresynchronized
withrespecttotheLOW-to-HIGHtransitionofRCLKA(RCLKB).
1
NOTE:
4093 tbl 08
The Write and Read Clock can be asynchronous or coincident.
1. For the purposes of this table, WENA2 and WENB2 = VIH.
2. The same selection sequence applies to reading from the registers. RENA1 and RENA2
(RENB1 and RENB2) are enabled and read is performed on the LOW-to-HIGH transition
of RCLKA (RCLKB).
Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read
Enables,RENA1,RENA2(RENB1,RENB2)areLOW,dataisreadfromArray
A(B)totheoutputregisterontheLOW-to-HIGHtransitionoftheReadClock,
RCLKA (RCLKB).
Figure 2. Writing to Offset Registers for FIFOs A and B
OCTOBER22,2008
6
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