Datasheet > 存储 > FIFO> IDT72V255LA15PFGI

IDT72V255LA15PFGI

更新时间： 2024-01-23 18:14:23

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
27页	436K
描述
FIFO, 8KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64

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技术参数
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IDT72V255LA15PFGI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	SLIM, TQFP-64	针数：	64
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.17
Is Samacsys：	N	最长访问时间：	10 ns
最大时钟频率 (fCLK)：	66.7 MHz	周期时间：	15 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	10 mm	内存密度：	147456 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	64	字数：	8192 words
字数代码：	8000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8KX18	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP64,.47SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.02 A	子类别：	FIFOs
最大压摆率：	0.055 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

IDT72V255LA15PFGI 数据手册

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IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™

8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

For serial programming, SEN together with LD on each rising edge of

WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel

programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused

toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge

of RCLK can be used to read the offsets in parallel from Qn regardless of

whetherserialorparalleloffsetloadinghasbeenselected.

DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault

settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023

withserialprogramming. Theflagsareupdatedaccordingtothetimingmode

anddefaultoffsetsselected.

The Partial Reset (PRS) also sets the read and write pointers to the first

locationofthememory. However,thetimingmode,partialflagprogramming

method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset

remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand

offsetsineffect. PRSisusefulforresettingadeviceinmid-operation,when

reprogrammingpartialflagswouldbeundesirable.

TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan

once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit

operationbysettingthereadpointertothefirstlocationofthememoryarray.

If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill

automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply

currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol

inputs)willimmediatelytakethedeviceoutofthepowerdownstate.

The IDT72V255LA/72V265LA are fabricated using IDT’s high speed

submicron CMOS technology.

DESCRIPTION (CONTINUED)

Therearetwopossibletimingmodesofoperationwiththesedevices:IDT

Standard mode and First Word Fall Through (FWFT) mode.

InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear

onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread

operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,

willshiftthewordfrominternalmemorytothedataoutputlines.

InFWFTmode,thefirstwordwrittentoanemptyFIFOis clockeddirectly

tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes

not have to be asserted foraccessingthe first word. However, subsequent

wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof

theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.

ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO

can provide, the FWFT timing mode permits depth expansion by chaining

FIFOs in series (i.e. the data outputs of one FIFO are connected to the

corresponding data inputs of the next). No external logic is required.

These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),

FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable

Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFand

FF functions are selectedinIDTStandardmode. The IR and OR functions

areselectedinFWFTmode. HF,PAEandPAFarealwaysavailableforuse,

irrespectiveoftimingmode.

PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin

memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag

switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two

defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127

or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset

at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith

the LD pin during Master Reset.

PARTIAL RESET (PRS) MASTER RESET (MRS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

DATA OUT (Q0 - Qn)

DATA IN (D0 - Dn)

IDT

72V255LA

72V265LA

RETRANSMIT (RT)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

FULL FLAG/INPUT READY (FF/IR)

HALF FULL FLAG (HF)

PROGRAMMABLE ALMOST-FULL (PAF)

4672 drw 03

Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO

1 234 5 6 7...27

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与IDT72V255LA15PFGI相关器件

型号	品牌	描述	获取价格	数据表
IDT72V255LA15PFGI8	IDT	FIFO, 8KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64	获取价格
IDT72V255LA15PFI	IDT	3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18	获取价格
IDT72V255LA15PFI9	IDT	FIFO, 8KX18, 10ns, Synchronous, CMOS, PQFP64, TQFP-64	获取价格
IDT72V255LA15TF	IDT	3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18	获取价格
IDT72V255LA15TF8	IDT	FIFO, 8KX18, 10ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64	获取价格
IDT72V255LA15TF9	IDT	FIFO, 8KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64	获取价格

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