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IDT72V245L15PFG

更新时间： 2024-02-22 13:08:01
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 216K
描述
FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64

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IDT72V245L15PFG 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, STQFP-64针数：64
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.42
Is Samacsys：N最长访问时间：10 ns
最大时钟频率 (fCLK)：66.7 MHz周期时间：15 ns
JESD-30 代码：S-PQFP-G64JESD-609代码：e0
长度：10 mm内存密度：73728 bit
内存集成电路类型：OTHER FIFO内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：64字数：4096 words
字数代码：4000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4KX18可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP64,.47SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.005 A子类别：FIFOs
最大压摆率：0.03 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：10 mmBase Number Matches：1

IDT72V245L15PFG 数据手册

 浏览型号IDT72V245L15PFG的Datasheet PDF文件第6页浏览型号IDT72V245L15PFG的Datasheet PDF文件第7页浏览型号IDT72V245L15PFG的Datasheet PDF文件第8页浏览型号IDT72V245L15PFG的Datasheet PDF文件第10页浏览型号IDT72V245L15PFG的Datasheet PDF文件第11页浏览型号IDT72V245L15PFG的Datasheet PDF文件第12页 
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes  
totheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+tSKEW  
afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess  
allotherwords,areadmustbeexecutedusingREN. TheRCLKLOWtoHIGH  
transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)  
willgoHIGHwithatrue read(RCLKwithREN=LOW),inhibitingfurtherread  
operations. REN is ignored when the FIFO is empty.  
SIGNALDESCRIPTIONS:  
INPUTS:  
DATA IN (D0 - D17)  
Datainputsfor18-bitwidedata.  
CONTROLS:  
RESET (RS)  
OUTPUTENABLE(OE)  
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOW  
state. During reset, both internal read and write pointers are set to the first  
location.Aresetisrequiredafterpower-upbeforeawriteoperationcantake  
place.TheHalf-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)will  
beresettoHIGHaftertRSF.TheProgrammableAlmost-EmptyFlag(PAE)will  
beresettoLOWaftertRSF. TheFullFlag (FF)willresettoHIGH. TheEmpty  
Flag(EF)willresettoLOWinIDTStandardmodebutwillresettoHIGHinFWFT  
mode. Duringreset,theoutputregisterisinitializedtoallzerosandtheoffset  
registersareinitializedtotheirdefaultvalues.  
WhenOutputEnable (OE)is enabled(LOW), the paralleloutputbuffers  
receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput  
databusisinahigh-impedancestate.  
LOAD (LD)  
The IDT72V205/72V215/72V225/72V235/72V245 devices contain two  
12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs. Whenthe  
Load(LD)pinissetLOWandWENissetLOW,dataontheinputsD0-D11is  
writtenintotheEmptyOffsetregisteronthefirstLOW-to-HIGHtransitionofthe  
Write Clock(WCLK). WhentheLD pinandWEN are heldLOWthendata is  
writtenintotheFullOffsetregisteronthesecondLOW-to-HIGHtransitionof  
WCLK.ThethirdtransitionofWCLKagainwritestotheEmptyOffsetregister.  
However,writingalloffsetregistersdoesnothavetooccuratonetime.One  
ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the  
FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,  
andWENisLOW,thenextoffsetregisterinsequenceiswritten.  
WRITE CLOCK (WCLK)  
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock  
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH  
transitionofWCLK.  
The Write andReadClocks canbe asynchronous orcoincident.  
WRITE ENABLE (WEN)  
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray  
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored  
in the RAM array sequentially and independently of any ongoing read  
operation.  
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK  
cycle.  
To prevent data overflow in the IDT Standard Mode, FF will go LOW,  
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,  
FFwillgoHIGHallowingawritetooccur. TheFFflagisupdatedontherising  
edgeofWCLK.  
LD  
WEN  
WCLK  
Selection  
Writingtooffsetregisters:  
EmptyOffset  
0
0
FullOffset  
0
1
1
1
0
1
NoOperation  
WriteIntoFIFO  
NoOperation  
Topreventdata overflow inthe FWFTmode, IR willgoHIGH, inhibiting  
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo  
LOWallowingawritetooccur. TheIRflagisupdatedontherisingedgeofWCLK.  
NOTE:  
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.  
1. The same selection sequence applies to reading from the registers. REN is enabled and  
read is performed on the LOW-to-HIGH transition of RCLK.  
READ CLOCK (RCLK)  
Figure 2. Writing to Offset Registers  
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead  
Clock(RCLK),whenOutputEnable(OE)is setLOW.  
The Write andReadClocks canbe asynchronous orcoincident.  
17  
0
11  
EMPTY OFFSET REGISTER  
READ ENABLE (REN)  
DEFAULT VALUE  
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput  
register on the rising edge of every RCLK cycle if the device is not empty.  
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand  
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain  
the previous data value.  
001FH (72V205) 003FH (72V215):  
007FH (72V225/72V235/72V245)  
11  
17  
0
FULL OFFSET REGISTER  
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst  
wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast  
wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting  
furtherreadoperations. RENisignoredwhentheFIFOisempty. Onceawrite  
isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated  
on the rising edge of RCLK.  
DEFAULT VALUE  
001FH (72V205) 003FH (72V215):  
007FH (72V225/72V235/72V245)  
4294 drw 04  
NOTE:  
1. Any bits of the offset register not being programmed should be set to zero.  
Figure 3. Offset Register Location and Default Values  
9
1...6789101112...25

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