IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION (TQFP & BGA PACKAGES)
Symbol
Name
I/O
Description
(1)
BE
*Big-Endian/
Little-Endian
I
DuringMasterReset, a LOWonBE willselectBig-Endianoperation. AHIGHonBE duringMasterResetwill
selectLittle-Endianformat.
D0–D17 DataInputs
I
Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D0–D17 are used. When in 9-bit mode, D0–D8 are used
andthe unusedinputs, D9–D17, shouldbe tiedLOW.
EF/OR EmptyFlag/
O
O
IntheIDTStandardmode, the EF functionis selected.EF indicates whetherornotthe FIFOmemoryis empty.In
FWFTmode,theOR functionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemoryis full. Inthe
FWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailableforwritingtotheFIFO
memory.
OutputReady
FF/IR
Full Flag/
Input Ready
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
I
I
I
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe
programmableflagsPAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions
asaserialinputforloadingoffsetregisters.
FWFT/SI FirstWordFall
Through/Serial In
HF
IP(1)
Half-FullFlag
O
I
HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
InterspersedParity
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
Paritymode. InterspersedParitycontrolonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.It
doesnoteffectthedatawrittentoandreadfromtheFIFO.
(1)
IW
InputWidth
Load
I
I
This pinselects the bus widthofthe write port. DuringMasterReset, whenIWis LOW, the write portwillbe
configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width.
LD
Thisisadualpurposepin.DuringMasterReset,thestateoftheLDinput,alongwithFSEL0andFSEL1,determines
oneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
beprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswritingtoandreadingfromthe
offsetregisters.
MRS
OE
MasterReset
I
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringMasterReset,the
FIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogrammable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency
timingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OutputEnable
OutputWidth
I
I
OEcontrolstheoutputimpedanceofQn.
This pinselects the bus widthofthe readport. DuringMasterReset, whenOWis LOW, the readportwillbeconfig-
ured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width.
(1)
OW
PAE
PAF
Programmable
Almost-EmptyFlag
O
O
I
PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyOffset
register. PAE goes HIGHifthe numberofwords inthe FIFOmemoryis greaterthanorequaltooffsetn.
PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedinthe
FullOffsetregister.PAFgoes LOWifthenumberoffreelocations intheFIFOmemoryis less thanorequaltom.
DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHonPFM
willselectSynchronousProgrammableflagtimingmode.
Programmable
Almost-FullFlag
(1)
PFM
Programmable
Flag Mode
PRS
PartialReset
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings are
allretained.
Q0–Q17 DataOutputs
O
Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are
used,andtheunusedoutputs,Q9-Q17shouldnotbeconnected.Outputsarenot5Vtolerantregardlessofthe
stateofOE.
REN
ReadEnable
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
RCLK/ ReadClock/
RD
If Synchronous operation of the read port has been selected, when enabled byREN, the rising edge of RCLK
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intothe offsetregisters is outputona risingedge ofRCLK. IfAsynchronous operationofthe readporthas been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operationofthe RCLK/RDinputis onlyavailable inthe BGApackage.
ReadStrobe
NOTE:
1. Inputs should not change state after Master Reset.
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