IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
TM
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 5 2K x9
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis
configuredduringmasterresetbythestateoftheBig-Endian(BE)pin.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionD8duringtheparallel
programmingoftheflagoffsets.IfNon-InterspersedParitymodeisselected,then
D8isassumedtobeavalidbitandD16andD17areignored.IPmodeisselected
duringMasterResetbythestateoftheIPinputpin.Thismodeisrelevantonly
whentheinputwidthis settox18mode.InterspersedParitycontrolonlyhas
aneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthe
data writtentoandreadfromthe FIFO.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
BoundaryScanArchitecture.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293arefabricatedusingIDT’shighspeedsubmicronCMOStechnology.
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
If synchronous PAE/PAF configuration is selected , the PAE is asserted
andupdatedonthe risingedge ofRCLKonlyandnotWCLK. Similarly, PAF
isassertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.The
modedesiredisconfiguredduringmasterresetbythestateoftheProgrammable
Flag Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmitoperationbysettingthereadpointertothefirstlocationofthememory
array. A zero-latency retransmit timing mode can be selected using the
RetransmittimingModepin(RM).DuringMasterReset,aLOWonRMwillselect
zero-latencyretransmit.AHIGHonRMduringMasterResetwillselectnormal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmitted will be placed on the output register with respect to the same
RCLK edge that initiated the retransmit based on RT being LOW.
RefertoFigure11and12forRetransmitTimingwithnormallatency.Refer
to Figure 13 and 14 for Retransmit Timing with zero-latency.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
useful when data is written into the FIFO in long word format (x18) and read
outoftheFIFOinsmallword(x9)format.IfBig-Endianmodeisselected,then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IW
OW
Write Port Width
Read Port Width
L
L
L
H
L
x18
x18
x9
x18
x9
H
H
x18
x9
H
x9
5
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