IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Forserialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadthe offsetregisters via Dn.REN togetherwithLD oneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
During Master Reset (MRS) the following events occur: the read and
write pointers are set to the first location of the FIFO. The FWFT pin selects
IDT Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing
beforePartialResetremainunchanged.Theflagsareupdatedaccordingtothe
timingmodeandoffsets ineffect.PRS is usefulforresettingadeviceinmid-
operation,whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
DESCRIPTION(CONTINUED)
not have to be asserted for accessing the first word. However, subsequent
words writtentotheFIFOdorequireaLOWonREN foraccess.Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs ofthe next). Noexternallogicis required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF (Programmable Almost-Fullflag). The EF and
FFfunctionsareselectedinIDTStandardmode.TheIRandORfunctionsare
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory.Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial.Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary.Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
Ifasynchronous PAE/PAFconfigurationisselected,thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR*)
READ CLOCK (RCLK/RD*)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
IDT
OUTPUT ENABLE (OE)
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
(x9 or x18) DATA IN (D0 - Dn)
(x9 or x18) DATA OUT (Q0 - Qn)
SERIAL CLOCK (SCLK)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
SERIAL ENABLE(SEN)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
4666 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
4
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