Datasheet > IDT72801L10TFG8

IDT72801L10TFG8

更新时间： 2024-01-17 17:34:12

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
16页	211K
描述
FIFO, 256X9, 6.5ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64

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IDT72801L10TFG8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.44
最长访问时间：	6.5 ns	周期时间：	10 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e3
长度：	10 mm	内存密度：	2304 bit
内存宽度：	9	功能数量：	2
端子数量：	64	字数：	256 words
字数代码：	256	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256X9	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	10 mm
Base Number Matches：	1

IDT72801L10TFG8 数据手册

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO^TM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

PIN DESCRIPTIONS

TheIDT72801/72811/72821/72831/72841/72851s twoFIFOs,referred descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorrespond-

to as FIFO A and FIFO B, are identical in every respect. The following ing signal names for FIFO B are provided in parentheses.

Symbol

DA0-DA8

DB0-DB8

RSA, RSB

Name

ADataInputs

BDataInputs

Reset

I/O

Description

9-bit data inputs to RAM array A.

9-bit data inputs to RAM array B.

When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to

the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go

LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.

WCLKA

WCLKB

WriteClock

Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write

enable(s)areasserted.

WENA1

WENB1

WriteEnable1

If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only Write

Enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO

oneveryLOW-to-HIGHtransitionWCLKA(WCLKB). Ifthe FIFOis configuredtohave twowrite enables,

WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data

will not be written into the FIFO ifFFA (FFB) is LOW.

WENA2/LDA

WENB2/LDB

WriteEnable2/

Load

FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB)

is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA (WENB2/LDB) is LOW

at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.

If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW

and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)

if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA

(LDB) is held

LOW to write or read the programmable flag offsets.

QA0-QA8

QB0-QB8

A Data Outputs

B Data Outputs

ReadClock

9-bit data outputs from RAM array A.

9-bit data outputs from RAM array B.

RCLKA

RCLKB

Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1

(RENB1) and RENA2 (RENB2) are asserted.

RENA1

RENB1

Read Enable 1

Read Enable 2

OutputEnable

EmptyFlag

When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every

LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.

RENA2

RENB2

When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every

LOW-to-HIGHtransitionofRCLKA(RCLKB). Data willnotbe readfromarrayA(B)ifthe EFA (EFB)is LOW.

OEA

OEB

When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the

outputs DA0-DA8(DB0-DB8)willbeinahigh-impedancestate.

EFA

EFB

When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.

When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).

PAEA

PAEB

Programmable

Almost-Empty

Flag

WhenPAEA (PAEB)is LOW, FIFOA(B)is almost-emptybasedonthe offsetprogrammedintothe

appropriateoffsetregister. Thedefaultoffsetatresetis Empty+7.PAEA (PAEB)is synchronizedto

RCLKA (RCLKB).

PAFA

PAFB

Programmable

Almost-FullFlag

WhenPAFA (PAFB)is LOW, FIFOA(B)is almost-fullbasedonthe offsetprogrammedintothe appropriate

offsetregister. The defaultoffsetatresetis Full-7. PAFA (PAFB)is synchronizedtoWCLKA(WCLKB).

FFA

FFB

VCC

Full Flag

When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.

When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).

+5V power supply pin.

Power

GND

Ground

0V ground pin.

1 234 5 6 7...16

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