Datasheet > IDT723641L15PQFG

IDT723641L15PQFG

更新时间： 2024-01-23 14:15:29

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
21页	216K
描述
FIFO, 1KX36, 11ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132

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IDT723641L15PQFG 数据手册

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IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICSOVERRECOMMENDEDRANGESOF

SUPPLYVOLTAGEANDOPERATINGFREE-AIRTEMPERATURE

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)

Commercial

IDT723631L15

IDT723641L15

IDT723651L15

Com’l & Ind’l⁽¹⁾

IDT723631L20

IDT723641L20

IDT723651L20

Symbol

Parameter

Min.

Max.

Min.

–

Max.

Unit

MHz

Clock Frequency, CLKA or CLKB

–

66.7

–

tCLK

Clock Cycle Time, CLKA or CLKB

tCLKH

tCLKL

tDS

Pulse Duration, CLKA or CLKB HIGH

Pulse Duration, CLKA or CLKB LOW

Setup Time, A0-A35 before CLKA↑and B0-B35 before CLKB↑

Setup Time, ENA to CLKA↑; ENB to CLKB↑

Setup Time, CSA, W/RA, and MBA to CLKA↑; CSB, W/RB and MBB to CLKB↑

Setup Time, RTM and RFM to CLKB↑

tENS1

tENS2

tRMS

7.5

6.5

(2)

tRSTS

tFSS

Setup Time, RST LOW before CLKA↑ or CLKB↑

Setup Time, FS0 and FS1 before RST HIGH

tSDS⁽³⁾

tSENS⁽³⁾

tDH

Setup Time, FS0/SD before CLKA↑

Setup Time, FS1/SEN before CLKA↑

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

Hold Time, ENA after CLKA↑; ENB after CLKB↑

Hold Time, CSA, W/RA, and MBA after CLKA↑; CSB, W/RB and MBB after CLKB↑

Hold Time, RTM and RFM after CLKB↑

tENH1

tENH2

tRMH

tRSTH

tFSH

(2)

Hold Time, RST LOW after CLKA↑ or CLKB↑

Hold Time, FS0 and FS1 after RST HIGH

Hold Time, FS1/SEN HIGH after RST HIGH

Hold Time, FS0/SD after CLKA↑

(3)

tSPH

(3)

tSDH

(3)

tSENH

Hold Time, FS1/SEN after CLKA↑

tSKEW1⁽⁴⁾Skew Time, between CLKA↑ and CLKB↑ for OR and IR

tSKEW2⁽⁴⁾Skew Time, between CLKA↑and CLKB↑ for AE and AF

NOTES:

1. Industrial temperature range product for 20ns is available as a standard device.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Only applies when serial load method is used to program flag Offset registers.

4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

5. Design simulated but not tested (typical values).

1...4 5 678 9 10...21

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STM32F103C8T6 替代型号

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