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IDT71V3559S75BGGI PDF预览

IDT71V3559S75BGGI

更新时间： 2024-02-15 17:35:17
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
28页 298K
描述
Synchronous ZBT SRAMs

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中文翻译

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IDT71V3559S75BGGI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.46
最长访问时间：7.5 nsJESD-30 代码：R-PBGA-B119
JESD-609代码：e1长度：22 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：119
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX18
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2.36 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IDT71V3559S75BGGI 数据手册

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128K x 36, 256K x 18,  
IDT71V3557S  
IDT71V3559S  
IDT71V3557SA  
IDT71V3559SA  
3.3V Synchronous ZBT™ SRAMs  
3.3V I/O, Burst Counter,  
Flow-Through Outputs  
Features  
it read or write.  
◆
128K x 36, 256K x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
The IDT71V3557/59 contain address, data-in and control signal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V3557/59  
to be suspended as long as necessary. All synchronous inputs are  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted  
when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will  
be completed. The data bus will tri-state one cycle after chip is de-  
selectedorawriteisinitiated.  
The IDT71V3557/59 have an on-chip burst counter. In the burst  
mode, the IDT71V3557/59 can provide four cycles of data for a single  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates  
the need to control OE  
◆
◆
◆
◆
◆
◆
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)  
Optional Boundary Scan JTAG Interface (IEEE 1149.1  
complaint)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine  
pitch ball grid array (fBGA)  
◆
Description  
TheIDT71V3557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are  
designed to eliminate dead bus cycles when turning the bus around  
between reads and writes, or writes and reads. Thus they have been  
given the name ZBTTM, or Zero Bus Turnaround.  
The IDT71V3557/59 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pin thinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle, andonthenextclockcycletheassociateddatacycleoccurs, be  
PinDescriptionSummary  
A
0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1  
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
TMS  
TDI  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
52 82 tb l 01  
FEBRUARY 2009  
1
©2009 Integrated Device Technology, Inc.  
DSC-5282/09  
1234567...28

中文翻译

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与IDT71V3559S75BGGI相关器件

型号 品牌 获取价格 描述 数据表
IDT71V3559S75BGI IDT

获取价格

 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S75BQ IDT

获取价格

 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S75BQG IDT

获取价格

 		Synchronous ZBT SRAMs
IDT71V3559S75BQGI IDT

获取价格

 		Synchronous ZBT SRAMs
IDT71V3559S75BQI IDT

获取价格

 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S75PF IDT

获取价格

 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S75PF8 IDT

获取价格

 		ZBT SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V3559S75PF9 IDT

获取价格

 		ZBT SRAM, 256KX18, 7.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V3559S75PFG IDT

获取价格

 		Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLA
IDT71V3559S75PFG8 IDT

获取价格

 		Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLA

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