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IDT71V3558SA166BQGI8 PDF预览

IDT71V3558SA166BQGI8

更新时间： 2024-01-21 02:38:57
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
28页 637K
描述
ZBT SRAM, 256KX18, 3.5ns, CMOS, PBGA165

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IDT71V3558SA166BQGI8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active包装说明：BGA, BGA165,11X15,40
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.26
Is Samacsys：N最长访问时间：3.5 ns
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
端子数量：165字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大待机电流：0.045 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.36 mA标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
Base Number Matches：1

IDT71V3558SA166BQGI8 数据手册

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IDT71V3556S/XS  
IDT71V3558S/XS  
IDT71V3556SA/XSA  
128K x 36, 256K x 18  
3.3V Synchronous ZBT SRAMs  
3.3V I/O, Burst Counter  
Pipelined Outputs  
IDT71V3558SA/XSA  
Description  
Features  
◆
TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit) synchronous SRAMS. They are designed to eliminate dead bus  
cycles when turning the bus around between reads and writes, or  
writes and reads. Thus, they have been given the name ZBTTM, or  
Zero Bus Turnaround.  
128K x 36, 256K x 18 memory configurations  
◆
Supports high performance system speed - 200 MHz (x18)  
(3.2 ns Clock-to-Data Access)  
Supports high performance system speed - 166 MHz (x36)  
◆
(3.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
Address and control signals are applied to the SRAM during one  
clock cycle, and two cycles later the associated data cycle occurs, be  
it read or write.  
cycles  
◆
Internally synchronized output buffer enable eliminates the  
The IDT71V3556/58 contain data I/O, address and control signal  
registers. Output enable is the only asynchronous signal and can be  
used to disable the outputs at any given time.  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
◆
◆
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58  
to be suspended as long as necessary. All synchronous inputs are  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
user to deselect the device when desired. If any one of these three are  
not asserted when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will be  
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected  
orawriteisinitiated.  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)  
Optional- Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
◆
◆
◆
◆
◆
◆
Pin Description Summary  
A
0
-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE  
1
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
Test Clock  
TDO  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5281 tbl 01  
OCTOBER 2010  
1
DSC-5281/11  
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
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