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IDT70V3399S166PRFG PDF预览

IDT70V3399S166PRFG

更新时间: 2024-11-19 21:01:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 222K
描述
Dual-Port SRAM, 128KX18, 3.6ns, CMOS, PQFP128, 14 X 20 MM X 1.4 MM, GREEN, PLASTIC, TQFP-128

IDT70V3399S166PRFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP128,.63X.87针数:128
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.32
最长访问时间:3.6 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):166 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G128JESD-609代码:e3
长度:20 mm内存密度:2359296 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端口数量:2端子数量:128
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP128,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.03 A
最小待机电流:3.15 V子类别:SRAMs
最大压摆率:0.5 mA最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT70V3399S166PRFG 数据手册

 浏览型号IDT70V3399S166PRFG的Datasheet PDF文件第2页浏览型号IDT70V3399S166PRFG的Datasheet PDF文件第3页浏览型号IDT70V3399S166PRFG的Datasheet PDF文件第4页浏览型号IDT70V3399S166PRFG的Datasheet PDF文件第5页浏览型号IDT70V3399S166PRFG的Datasheet PDF文件第6页浏览型号IDT70V3399S166PRFG的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
256/128K x 18  
SYNCHRONOUS  
IDT70V3319/99S  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Š
Features:  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Dual Cycle Deselect (DCD) for Pipelined Output mode  
LVTTL- compatible, single 3.3V (±150mV) power supply  
for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 133MHz.  
Available in a 128-pin Thin Quad Flatpack, 208-pin fine  
pitch Ball Grid Array, and 256-pin Ball  
GridArray  
Supports JTAG features compliant to IEEE 1149.1  
Due to limited pin count, JTAG is not supported on the  
128-pin TQFP package  
High-speed data access  
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Industrial: 4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Due to limited pin count PL/FToption is not supported  
on the 128-pin TQFP package. Device is pipelined  
outputs only on each port.  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 6ns cycle time, 166MHzoperation(6Gbps bandwidth)  
– Fast 3.6ns clock to data out  
– 1.7ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 166MHz  
Data input, address, byte enable and control registers  
Green parts available, see ordering information  
Functional Block Diagram  
UBL  
UBR  
LBL  
LBR  
FT/PIPE  
L
1b 0b  
b
1a 0a  
a
0a 1a  
a
0b 1b  
b
FT/PIPER  
1/0  
1/0  
R/WL  
R/WR  
CE0L  
CE0R  
1
1
CE1R  
CE1L  
B
B
B B  
0
W W  
0
W W  
0
L
1
L
1
0
R
R
1/0  
1/0  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
OEL  
OER  
,
0a 1a  
1b 0b 1a 0a  
ab  
0b 1b  
ba  
0/1  
FT/PIPE  
R
FT/PIPE  
L
0/1  
256K x 18  
MEMORY  
ARRAY  
I/O0R - I/O17R  
Din_L  
I/O0L - I/O17L  
Din_R  
,
CLKR  
CLKL  
(1)  
L
(1)  
A
17L  
A
A
17R  
0R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A0L  
ADDR_R  
ADDR_L  
REPEAT  
ADS  
CNTEN  
REPEAT  
ADS  
CNTEN  
R
R
L
R
L
5623 tbl 01  
TDI  
TCK  
TMS  
TRST  
NOTE:  
1. A17 is a NC for IDT70V3399.  
JTAG  
TDO  
JULY 2008  
1
DSC 5623/8  
©2008 Integrated DeviceTechnology,Inc.  

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