Datasheet > IDT70P24

IDT70P24

更新时间： 2024-02-10 03:01:29

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
23页	294K
描述
HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT, 8/4K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT70P24 数据手册

HIGH-SPEED 1.8V

8/4K x 18 DUAL-PORT

8/4K x 16 DUAL-PORT

STATIC RAM

ADVANCED

IDT70P35/34L

IDT70P25/24L

Features

◆

select when cascading more than one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

BUSY and Interrupt Flag

On-chip port arbitration logic

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

IDT70P35/34L (IDT70P25/24L)

– Commercial: 20/25ns (max.)

Full on-chip hardware support of semaphore signaling

between ports

– Industrial: 25ns (max.)

Low-power operation

◆

Fully asynchronous operation from either port

LVTTL-compatible, single 1.8V (±100mV) power supply

Available in a 100-pin Thin Quad Flatpack (TQFP) package,

100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin

0.5mm pitch BGA (fpBGA)

IDT70P35/34L (IDT70P25/24L)

Active:30.6mW(typ.)

Standby: 5.4mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT70P35/34L (IDT70P25/24L) easily expands data bus

width to 36 bits (32 bits) or more using the Master/Slave

◆

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

R/W

UBL

CE^L

OEL

(5)

(4)

I/O9R-I/O17R

I/O9L-I/O17L

I/O

Control

I/O

Control

(4)

I/O0R-I/O8R

I/O0L-I/O8L

BUSY ^(2,3)

(2,3)

BUSY

(1)

12L

(1)

12R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(3)

INTR

M/S

INTL

5683 drw 01

NOTES:

1. A12 is a NC for IDT70P34 and IDT70P24.

2. (MASTER): BUSY is output; (SLAVE): BUSY is input.

3. BUSY outputs and INT outputs are non-tri-stated push-pull.

4. I/O0x - I/O7x for IDT70P25/24.

5. I/O8x - I/O15x for IDT70P25/24.

FEBRUARY 2004

DSC-5683/2

12 3 4 5 6 7...23

中文翻译

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