Datasheet > IDT70P247L55BYI

IDT70P247L55BYI

更新时间： 2024-01-25 00:48:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
23页	295K
描述
VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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IDT70P247L55BYI 数据手册

PRELIMINARY

VERY LOW POWER 1.8V

8K/4K x 16 DUAL-PORT

STATIC RAM

IDT70P257/247L

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

M/S = VDD for BUSY output flag on Master

M/S = V^SSfor BUSY input on Slave

Input Read Register

Output Drive Register

BUSY and Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 1.8V (±100mV) power supply

Available in 100 Ball 0.5mm-pitch BGA

Industrial temperature range (-40°C to +85°C)

◆

– Industrial: 55ns (max.)

Low-power operation

IDT70P257/247L

Active:27mW(typ.)

Standby: 3.6µW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT70P257/247 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading more

than one device

◆

Functional Block Diagram

R/W

UBR

UBL

LBL

CEL

OEL

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

BUSY ^(2,3)

(2,3)

BUSY

(1)

12R

(1)

12L

Address

Decoder

Address

Decoder

MEMORY

ARRAY

A0R

R/W

ODR

INPUT

READ REGISTER

AND

R/W

OUTPUT

DRIVE REGISTER

ODR

IRR0,IRR1

SFEN

R/W

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INTR

(3)

SEM

(3)

M/S

INTL

5684 drw 01

NOTES:

1. A¹²X is a NC for IDT70P247.

2. (MASTER): BUSY is output; (SLAVE): BUSY is input.

3. BUSY outputs and INT outputs are non-tri-stated push-pull.

FEBRUARY 2004

DSC-5684/1

12 3 4 5 6 7...23

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