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IDT5T2010BBI PDF预览

IDT5T2010BBI

更新时间: 2024-01-17 15:28:53
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路
页数 文件大小 规格书
23页 157K
描述
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK

IDT5T2010BBI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC68,.4SQ,20针数:68
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.85Is Samacsys:N
系列:5T输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-N68JESD-609代码:e0
长度:10 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.008 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:68实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC68,.4SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):240电源:1.5/2.5,2.5 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.1 ns
座面最大高度:1 mm子类别:Clock Driver
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mm最小 fmax:250 MHz
Base Number Matches:1

IDT5T2010BBI 数据手册

 浏览型号IDT5T2010BBI的Datasheet PDF文件第4页浏览型号IDT5T2010BBI的Datasheet PDF文件第5页浏览型号IDT5T2010BBI的Datasheet PDF文件第6页浏览型号IDT5T2010BBI的Datasheet PDF文件第8页浏览型号IDT5T2010BBI的Datasheet PDF文件第9页浏览型号IDT5T2010BBI的Datasheet PDF文件第10页 
IDT5T2010  
INDUSTRIALTEMPERATURERANGE  
2.5VZERODELAYPLLCLOCKDRIVER TERACLOCK  
INPUT/OUTPUTSELECTION(1)  
Input  
Output  
Input  
Output  
2.5VLVTTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
eHSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
HSTL DSE  
HSTL DSE  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
HSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
1.8VLVTTL  
HSTL DSE  
HSTL DSE  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
NOTE:  
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the  
REF[1:0] /VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2. Differential  
(DIF) inputs are used only in differential mode.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
VIHH  
Parameter  
Test Conditions  
Min.  
Max  
Unit  
V
Input HIGH Voltage Level(1)  
Input MID Voltage Level(1)  
InputLOWVoltageLevel(1)  
3-Level Inputs Only  
3-Level Inputs Only  
3-Level Inputs Only  
VIN = VDD  
VDD – 0.4  
VIMM  
VDD/2 – 0.2 VDD/2 + 0.2  
V
VILL  
0.4  
200  
+50  
V
HIGH Level  
MID Level  
LOW Level  
I3  
3-LevelInputDCCurrent  
(RxS, TxS, DS[1:0])  
VIN = VDD/2  
–50  
–200  
–100  
µA  
µA  
VIN = GND  
IPU  
Input Pull-Up Current (PE)  
VDD = Max., VIN = GND  
NOTE:  
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,  
the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved.  
7

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