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IDT5T2010BBI

更新时间： 2024-02-04 12:09:57

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器逻辑集成电路
页数	文件大小	规格书
23页	157K
描述
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK

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IDT5T2010BBI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN, LCC68,.4SQ,20	针数：	68
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.85	Is Samacsys：	N
系列：	5T	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQCC-N68	JESD-609代码：	e0
长度：	10 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.008 A	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	68	实输出次数：	10
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装等效代码：	LCC68,.4SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	240	电源：	1.5/2.5,2.5 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.1 ns
座面最大高度：	1 mm	子类别：	Clock Driver
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	10 mm	最小 fmax：	250 MHz
Base Number Matches：	1

IDT5T2010BBI 数据手册

IDT5T2010

INDUSTRIALTEMPERATURERANGE

2.5VZERODELAYPLLCLOCKDRIVER TERACLOCK

PINDESCRIPTION,CONTINUED

Symbol

REF_SEL

nsOE

I/O

Type

LVTTL⁽¹⁾

Description

Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.

Synchronousoutputenable. WhennsOEisHIGH,nQ[1:0]aresynchronouslystopped. OMODEselectswhethertheoutputsaregated

LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH, the

nQ[1:0] is stopped in a HIGH/LOW state. When OMODE is LOW, the outputs are tri-stated. Set nsOE LOW for normal operation.

QFB

nQ[1:0]

RxS

TxS

Adjustable⁽²⁾Feedbackclockoutput

Adjustable⁽²⁾Complementaryfeedbackclockoutput

Adjustable⁽²⁾Fivebanksoftwooutputs

3-Level⁽³⁾

Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input

Setsthedrivestrengthoftheoutputdriversandfeedbackinputstobe2.5VLVTTL(HIGH),1.8VLVTTL(MID)orHSTL/eHSTL(LOW)

compatible. UsedinconjuctionwithVDDQ tosettheinterfacelevels.

LVTTL⁽¹⁾

Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference

clock(hasinternalpull-up).

nF[2:1]

FBF[2:1]

LVTTL⁽¹⁾

3-Level⁽³⁾

LVTTL⁽¹⁾

Functionselectinputsfordivide-by-2, divide-by-4, zerodelay, orinvertoneachbank(SeeControlSummarytable)

Functionselectinputsfordivide-by-2, divide-by-4, zerodelay, orinvertonthefeedbackbank(SeeControlSummarytable)

Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeeVCOFrequencyRangeSelect.)

3-levelinputsforfeedbackinputdividerselection(SeeDivideSelectiontable)

DS[1:0]

PLL_EN

PLLenable/disablecontrol. SetLOWfornormaloperation. WhenPLL_ENisHIGH,thePLLisdisabledandREF[1:0] goestoalloutputs.

Powerdowncontrol. WhenPDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhethertheoutputs

are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/

HIGH, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a LOW/HIGH state. When OMODE is

LOW, theoutputsaretri-stated. SetPDHIGHfornormaloperation.

LOCK

LVTTL

PLLlockindicationsignal. HIGHindicateslock. LOWindicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtothe

inputs. Theoutputwillbe2.5VLVTTL.

OMODE

LVTTL⁽¹⁾

Outputdisablecontrol. Determinestheoutputs'disablestate. UsedinconjunctionwithnsOEandPD. (SeeOutputEnable/Disableand

Powerdowntables.)

VDDQ

VDD

PWR

Powersupplyforoutputbuffers. Whenusing2.5VLVTTL,VDDQshouldbeconnectedtoVDD.

Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry

Ground

GND

NOTES:

1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.

2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.

3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.

OUTPUTENABLE/DISABLE

nsOE

OMODE

Output

NormalOperation

Tri-State

VCOFREQUENCYRANGESELECT

FS⁽¹⁾

LOW

Min.

Max.

125

Unit

MHz

Gated⁽¹⁾

HIGH

100

250

NOTE:

1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the

nQ[1:0] is stopped in a HIGH/LOW state.

1. The level to be set on FS is determined by the nominal operating frequency of the

VCO. The VCO frequency (F^NOM) always appears at nQ[1:0] outputs when they are

operated in their undivided modes. The frequency appearing at the REF[1:0] and

REF[1:0] /VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB

are undivided and DS[1:0] = MM. The frequency of REF[1:0] and REF[1:0] /VREF[1:0]

and FB and FB/VREF2 inputs will be FNOM/2 or FNOM/4 when the part is configured for

frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM.

Using the DS[1:0] inputs allows a different method for frequency multiplication (see

Divide Selection table).

POWERDOWN

OMODE

Output

NormalOperation

Tri-State

Gated⁽¹⁾

NOTE:

1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the

nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a

LOW/HIGH state.

1 2 3 456 7 8...23

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IDT5T2010BBI8	IDT	PLL Based Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PBGA144, PLAST	获取价格
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IDT5T2010NLGI8	IDT	PLL Based Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC68, PLASTI	获取价格
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