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IDT29FCT520AE PDF预览

IDT29FCT520AE

更新时间: 2024-10-04 22:48:15
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 62K
描述
MULTILEVEL PIPELINE REGISTER

IDT29FCT520AE 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, FL24,.4
针数:24Reach Compliance Code:not_compliant
风险等级:5.89其他特性:MULTIPLEXED OUTPUT; ICC SPECIFIED @ 5MHZ
边界扫描:NO外部数据总线宽度:8
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:15.4 mm低功率模式:NO
端子数量:24最高工作温度:70 °C
最低工作温度:输出数据总线宽度:8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:FL24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:DSP Peripherals
最大压摆率:21.8 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, PIPELINE REGISTER

IDT29FCT520AE 数据手册

 浏览型号IDT29FCT520AE的Datasheet PDF文件第2页浏览型号IDT29FCT520AE的Datasheet PDF文件第3页浏览型号IDT29FCT520AE的Datasheet PDF文件第4页浏览型号IDT29FCT520AE的Datasheet PDF文件第5页浏览型号IDT29FCT520AE的Datasheet PDF文件第6页浏览型号IDT29FCT520AE的Datasheet PDF文件第7页 
IDT29FCT520A  
IDT29FCT520B  
IDT29FCT520C  
MULTILEVEL  
PIPELINE REGISTER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• Equivalent to AMD’s Am29520 bipolar Multilevel Pipeline  
Register in pinout/function, speed and output drive over  
full temperature and voltage supply extremes  
• Four 8-bit high-speed registers  
• Dual two-level or single four-level push-only stack  
operation  
• All registers available at multiplexed output  
• Hold, transfer and load instructions  
• Provides temporary address or data storage  
• IOL = 48mA (commercial), 32mA (military)  
• CMOS power levels (1mW typ. static)  
• Substantially lower input current levels than AMD’s  
bipolar (5µA typ.)  
TheIDT29FCT520A/B/Ccontainsfour8-bitpositive edge-  
triggered registers. These may be operated as a dual 2-level  
or as a single 4-level pipeline. A single 8-bit input is provided  
and any of the four registers is available at the 8-bit, 3-state  
output.  
In the IDT29FCT520A/B/C when data is entered into the  
first level (I = 2 or I = 1), the existing data in the first level is  
moved to the second level. Transfer of data to the second  
level is achieved using the 4-level shift instruction (I = 0). This  
transfer also causes the first level to change.  
• TTL input and output level compatible  
• CMOS output level compatible  
• Manufactured using advanced CMOS processing  
• Available in 300 mil plastic and hermetic DIP, as well as  
LCC, SOIC and CERPACK  
• Product available in Radiation Tolerant and Radiation  
Enhanced versions  
• Military product compliant to MIL-STD-883, Class B  
FUNCTIONAL BLOCK DIAGRAMS  
D0 -D7  
8
MUX  
2
I0,I1  
REGISTER  
CONTROL  
OCTAL REG. A1  
OCTAL REG. B1  
OCTAL REG. B2  
1
CLK  
OCTAL REG. A2  
2
S0 ,S1  
MUX  
OE  
8
2620 drw 01  
Y0 -Y7  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1992  
1992 Integrated Device Technology, Inc.  
7.2  
DSC-4608/2  
1

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Pipeline Register, 8-Bit, CMOS, CDIP24, CERDIP-24