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IDT2309A-1HPGGI8 PDF预览

IDT2309A-1HPGGI8

更新时间: 2024-10-03 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 53K
描述
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, LEAD FREE, TSSOP-16

IDT2309A-1HPGGI8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:LEAD FREE, TSSOP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.6
Is Samacsys:N系列:2309
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:8.7 ns
传播延迟(tpd):8.7 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:133 MHzBase Number Matches:1

IDT2309A-1HPGGI8 数据手册

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IDT2309A  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five and one bank of  
four outputs  
The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Separate output enable for each output bank  
• Output Skew < 250ps  
• Low jitter <200 ps cycle-to-cycle  
• IDT2309A-1 for Standard Drive  
• IDT2309A-1H for High Drive  
The IDT2309A is a 16-pin version of the IDT2305A. The IDT2309A  
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.  
The-1Hversionofthisdeviceoperatesupto133MHzfrequencyandhas  
higher drive than the -1 device. All parts have on-chip PLLs which lock  
to an input clock on the REF pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad. In the absence of an input clock, the  
IDT2309Aenterspowerdown. Inthismode,thedevicewilldrawlessthan  
• No external RC network required  
• Operates at 3.3V VDD  
• Available in SOIC and TSSOP packages  
12µAforCommercialTemperaturerangeandlessthan2AforIndustrial  
temperature range, and the outputs are tri-stated.  
The IDT2309A is characterized for both Industrial and Commercial  
operation.  
FUNCTIONALBLOCKDIAGRAM  
16  
CLKOUT  
2
CLKA1  
PLL  
1
REF  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
S2  
Control  
Logic  
9
S1  
6
CLKB1  
7
CLKB2  
10  
CLKB3  
11  
CLKB4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
JULY 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC - 6588/3  

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