Datasheet
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR + INTEGRATED SERIES RESISTOR
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator and Internal series resistor on differential outputs,
PCIe Gen 1 compliant
Key Specifications:
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 250ps
+/- 100ppm frequency accuracy on CPU & SRC
clocks
Output Features:
•
•
•
2 - CPU differential low power push-pull pairs
7 - SRC differential low power push-pull pairs
Features/Benefits:
1 - CPU/SRC selectable differential low power push-pull
pair
•
Does not require external pass transistor for voltage
regulator
•
1 - SRC/DOT selectable differential low power push-pull
pair
•
•
•
•
Integrated series resistors on differential outputs,
Zo=50W
•
•
•
•
5 - PCI, 33MHz
Supports spread spectrum modulation, default is 0.5%
down spread
1 - PCI_F, 33MHz free running
1 - USB, 48MHz
Uses external 14.318MHz crystal, external crystal
load caps are required for frequency tuning
1 - REF, 14.318MHz
One differential push-pull pair selectable between
SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
Pin Configuration
FSLC2 FSLB1 FSLA1
PCICLK0/CR#_A 1
VDDPCI 2
56 SCLK
55 SDATA
54 FSLC/TEST_SEL/REF0
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUCLKT0
45 CPUCLKC0
44 GNDCPU
43 CPUCLKT1
42 CPUCLKC1
41 VDDCPUI/O
CPU
SRC
PCI
REF
USB
MHz
DOT
MHz
MHz
MHz
MHz
MHz
B0b7
B0b6
B0b5
PCICLK1/CR#_B 3
PCICLK2/LTE 4
PCICLK3 5
PCICLK4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
33.33 14.318 48.00
Reserved
96.00
VDD96I/O 12
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
DOTT_96/SRCCLKT0 13
DOTC_96/SRCCLKC0 14
GND 15
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
VDD 16
specifications in the Input/Supply/Common Output Parameters Table for correct values.
17
40 NC
SRCCLKT1/SE1
SRCCLKC1/SE2 18
GND 19
39 CPUCLKT2_ITP/SRCCLKT8
38 CPUCLKC2_ITP/SRCCLKC8
37 VDDSRCI/O
VDDPLL3I/O 20
SRCCLKT2/SATACLKT 21
SRCCLKC2/SATACLKC 22
GNDSRC 23
36 SRCCLKT7/CR#_F
35 SRCCLKC7/CR#_E
34 GNDSRC
SRCCLKT3/CR#_C 24
SRCCLKC3/CR#_D 25
VDDSRCI/O 26
33 SRCCLKT6
32 SRCCLKC6
31 VDDSRC
SRCCLKT4 27
SRCCLKC4 28
30 PCI_STOP#/SRCCLKT5
29 CPU_STOP#/SRCCLKC5
56-SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
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