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9LPRS545BFLF PDF预览

9LPRS545BFLF

更新时间: 2023-03-15 00:00:00
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
17页 215K
描述
Microprocessor Circuit, PDSO48, 0.300 INCH, MO-118, SSOP-48

9LPRS545BFLF 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9LPRS545  
Datasheet  
48-pin CK505 for Intel Systems  
Recommended Application:  
Features/Benefits:  
48-pin Low Cost CK505 w/fully integrated VREG and series  
resistors on differential outputs  
Supports spread spectrum modulation, default is 0.5%  
down spread  
Uses external 14.318MHz crystal, external crystal load  
caps are required for frequency tuning  
Output Features:  
Integrated Series Resistors on differential outputs  
2 - CPU differential push-pull pairs  
Not recommended for new designs.The last time  
buy date for this product is 5/19/2011. Please refer  
toPDNK-10-18.  
4 - SRC differential push-pull pairs  
1 - CPU/SRC selectable differential push-pull pair  
1 - SRC/DOT selectable differential push-pull pair  
1- SRC/Stop_Inputs selectable differential push-pull pair  
1 - 25MHz SE1 output for Wake-on-Lan applications  
3 - PCI, 33MHz  
1 - USB, 48MHz  
Table 1: CPU Frequency Select Table  
FSLC2 FSLB1 FSLA1  
1 - REF, 14.31818MHz  
CPU  
MHz  
SRC  
MHz  
PCI  
REF  
MHz  
USB  
MHz  
DOT  
MHz  
MHz  
B0b7  
B0b6  
B0b5  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66  
133.33  
200.00  
166.66  
333.33  
100.00  
400.00  
Key Specifications:  
CPU outputs cycle-cycle jitter < 85ps  
SRC output cycle-cycle jitter < 125ps  
PCI outputs cycle-cycle jitter < 250ps  
+/-100ppm frequency accuracy on all clocks  
100.00  
33.33 14.318 48.00  
96.00  
Reserved  
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in  
the Input/Supply/Common Output Parameters Table for correct values.  
Also refer to the Test Clarification Table.  
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS  
specifications in the Input/Supply/Common Output Parameters Table for correct values.  
Pin Configuration  
PCI0/CR#_A  
VDDPCI  
SCLK  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
SDATA  
2
PCI4/SRC5_EN  
PCI_F5/ITP_EN  
GNDPCI  
REF0/FSLC/TEST_SEL  
VDDREF  
3
4
X1  
5
VDD48  
X2  
6
USB_48MHz/FSLA  
GND48  
GNDREF  
7
FSLB/TEST_MODE  
CK_PWRGD/PD#  
VDDCPU  
8
VDD96_IO  
9
DOT96T_LPR/SRCT0_LPR  
DOT96C_LPR/SRCC0_LPR  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CPUT0_LPR  
CPUC0_LPR  
VDD  
GNDCPU  
SE1  
CPUT1_LPR_F  
CPUC1_LPR_F  
VDDCPU_IO  
GND  
SRCT2_LPR/SATAT_LPR  
SRCC2_LPR/SATAC_LPR  
GNDSRC  
CPUT2_ITP_LPR/SRCT8_LPR  
CPUC2_ITP_LPR/SRCC8_LPR  
VDDSRC_IO  
SRCT3_LPR/CR#_C  
SRCC3_LPR/CR#_D  
VDDSRC_IO  
SRCT7_LPR/CR#_F  
SRCC7_LPR/CR#_E  
GNDSRC  
SRCT4_LPR  
SRCC4_LPR  
VDDSRC  
CPU_STOP#/SRCC5_LPR  
PCI_STOP#/SRCT5_LPR  
48-SSOP/TSSOP  
* Internal Pull-Up Resistor  
** Internal Pull-Down Resistor  
1479A—07/28/09  
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.  
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.  

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