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8S89874BKILFT PDF预览

8S89874BKILFT

更新时间: 2024-02-07 09:25:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路PC
页数 文件大小 规格书
19页 751K
描述
1:2 Differential-to-LVPECL Buffer/Divider

8S89874BKILFT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:VFQFPN
包装说明:VFQFN-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.72
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/1206300.2.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=1206300
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=12063003D View:https://componentsearchengine.com/viewer/3D.php?partID=1206300
Samacsys PartID:1206300Samacsys Image:https://componentsearchengine.com/Images/9/8S89874BKILFT.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/2/8S89874BKILFT.jpgSamacsys Pin Count:17
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:16 Lead VFQFNSamacsys Released Date:2020-01-16 13:37:31
Is Samacsys:N系列:8S
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-XQCC-N16
JESD-609代码:e3长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:16实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC16,.12SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3 VProp。Delay @ Nom-Sup:0.84 ns
传播延迟(tpd):0.84 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.015 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:3 mm
最小 fmax:2000 MHzBase Number Matches:1

8S89874BKILFT 数据手册

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1:2 Differential-to-LVPECL Buffer/Divider  
ICS8S89874I  
DATA SHEET  
General Description  
Features  
The ICS8S89874I is a high speed 1:2 Differential-to- LVPECL Buffer/  
Divider. The ICS8S89874I has a selectable ÷1, ÷2, ÷4, ÷8, ÷16  
output divider, which allows the device to be used as either a 1:2  
fanout buffer or frequency divider. The clock input has internal  
termination resistors, allowing it to interface with several differential  
signal types while minimizing the number of required external  
components. The device is packaged in a small, 3mm x 3mm  
VFQFN package, making it ideal for use on space-constrained  
boards.  
Two LVPECL/ECL output pairs  
Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8,  
÷16  
IN, nIN input can accept the following differential input levels:  
LVPECL, LVDS, CML  
Output frequency: 2GHz (maximum)  
Output skew: 15ps (maximum)  
Part-to-part skew: 250ps (maximum)  
Additive phase jitter, RMS: 0.20ps (typical)  
LVPECL supply voltage range: 2.375V to 3.63V  
ECL supply voltage range: -3.63V to -2.375V  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Pin Assignment  
Block Diagram  
Pullup  
S2  
16 15 14 13  
Q0  
nQ0  
Q1  
12  
1
2
3
IN  
Pullup  
VT  
11  
nRESET  
Enable  
FF  
10 VREF_AC  
Q0  
nQ1  
4
nIN  
9
Enable  
MUX  
5
6
7
8
0
nQ0  
1
Q1  
IN  
50  
VT  
00 ÷2  
01 ÷4  
10 ÷8  
11 ÷16  
nQ1  
ICS8S89874I  
16-Lead VFQFN  
3mm x 3mm x 0.925mm package body  
50Ω  
nIN  
S0  
S1  
Pullup  
Pullup  
K Package  
Top View  
Decoder  
VREF_AC  
ICS8S89874BKI REVISION A OCTOBER 22, 2010  
1
©2010 Integrated Device Technology, Inc.  

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